riscv/rocket-chip
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dcache fix TinyConfig

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This commit is contained in:
Wesley W. Terpstra
2016-11-18 19:50:34 -08:00
parent d1328a6b6f
commit 452bb2fc80
1 changed files with 10 additions and 2 deletions
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12
src/main/scala/rocket/dcache.scala
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@@ -254,7 +254,11 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu
val access_address = s2_req.addr
val a_size = s2_req.typ
val a_data = Fill(beatWords, pstore1_storegen.data)
val acquire = edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
val acquire = if (edge.manager.anySupportAcquire) {
edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
} else {
Wire(new TLBundleA(edge.bundle))
}
val get = edge.Get(a_source, access_address, a_size)._2
val put = edge.Put(a_source, access_address, a_size, a_data)._2
val atomics = if (edge.manager.anySupportLogical) {
@@ -370,12 +374,16 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu
b = probe_bits,
reportPermissions = TLPermissions.NtoN)
val voluntaryReleaseMessage = edge.Release(
val voluntaryReleaseMessage = if (edge.manager.anySupportAcquire) {
edge.Release(
fromSource = UInt(maxUncachedInFlight - 1),
toAddress = probe_bits.address,
lgSize = lgCacheBlockBytes,
shrinkPermissions = s2_shrink_param,
data = s2_data)._2
} else {
Wire(new TLBundleC(edge.bundle))
}
val probeResponseMessage = Mux(!s2_prb_ack_data,
edge.ProbeAck(