dcache fix TinyConfig
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d1328a6b6f
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@ -254,7 +254,11 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu
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val access_address = s2_req.addr
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val access_address = s2_req.addr
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val a_size = s2_req.typ
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val a_size = s2_req.typ
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val a_data = Fill(beatWords, pstore1_storegen.data)
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val a_data = Fill(beatWords, pstore1_storegen.data)
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val acquire = edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
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val acquire = if (edge.manager.anySupportAcquire) {
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edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
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} else {
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Wire(new TLBundleA(edge.bundle))
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}
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val get = edge.Get(a_source, access_address, a_size)._2
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val get = edge.Get(a_source, access_address, a_size)._2
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val put = edge.Put(a_source, access_address, a_size, a_data)._2
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val put = edge.Put(a_source, access_address, a_size, a_data)._2
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val atomics = if (edge.manager.anySupportLogical) {
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val atomics = if (edge.manager.anySupportLogical) {
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@ -370,12 +374,16 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu
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b = probe_bits,
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b = probe_bits,
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reportPermissions = TLPermissions.NtoN)
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reportPermissions = TLPermissions.NtoN)
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val voluntaryReleaseMessage = edge.Release(
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val voluntaryReleaseMessage = if (edge.manager.anySupportAcquire) {
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edge.Release(
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fromSource = UInt(maxUncachedInFlight - 1),
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fromSource = UInt(maxUncachedInFlight - 1),
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toAddress = probe_bits.address,
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toAddress = probe_bits.address,
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lgSize = lgCacheBlockBytes,
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lgSize = lgCacheBlockBytes,
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shrinkPermissions = s2_shrink_param,
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shrinkPermissions = s2_shrink_param,
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data = s2_data)._2
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data = s2_data)._2
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} else {
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Wire(new TLBundleC(edge.bundle))
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}
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val probeResponseMessage = Mux(!s2_prb_ack_data,
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val probeResponseMessage = Mux(!s2_prb_ack_data,
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edge.ProbeAck(
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edge.ProbeAck(
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