riscv/rocket-chip
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log2ceil

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This commit is contained in:
Henry Cook 2015-10-06 18:22:23 -07:00
parent 8173695800
commit 4508666d96
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/tlb.scala
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@ -11,7 +11,7 @@ case object NTLBEntries extends Field[Int]
trait HasTLBParameters extends HasAddrMapParameters { trait HasTLBParameters extends HasAddrMapParameters {
val entries = p(NTLBEntries) val entries = p(NTLBEntries)
val camAddrBits = ceil(log(entries)/log(2)).toInt val camAddrBits = log2Ceil(entries)
val camTagBits = asIdBits + vpnBits val camTagBits = asIdBits + vpnBits
} }