diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index a3b1e4ea..c53904fc 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -7,7 +7,7 @@ object Constants { val HAVE_RVC = false val HAVE_FPU = true - val HAVE_VEC = false + val HAVE_VEC = true val BR_N = UFix(0, 4); val BR_EQ = UFix(1, 4); diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 4683febc..d44c88c5 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -301,10 +301,10 @@ object rocketCtrlDecode VFSSTD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N), VFSSTW-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N), - VENQCMD-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,Y), - VENQIMM1-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,Y), - VENQIMM2-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,Y), - VENQCNT-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,Y), + VENQCMD-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), + VENQIMM1-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), + VENQIMM2-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), + VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VWAITXCPT-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y), VWAITKILL-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y)) } diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala index 2423e426..62f7f8c5 100644 --- a/rocket/src/main/scala/ctrl_vec.scala +++ b/rocket/src/main/scala/ctrl_vec.scala @@ -10,6 +10,7 @@ class ioCtrlDpathVec extends Bundle val valid = Bool(INPUT) val inst = Bits(32, INPUT) val appvl0 = Bool(INPUT) + val pfq = Bool(INPUT) val wen = Bool(OUTPUT) val fn = Bits(1, OUTPUT) val sel_vcmd = Bits(3, OUTPUT) @@ -69,74 +70,80 @@ class rocketCtrlVec extends Component // | | | | | vpfcmdq // | | | | | | vpfximm1q // | | | | | | | vpfximm2q - // wen | | | | | | | | vpfcntq - // val vcmd vimm vimm2 | fn | | | | | | | | | fence_cv - // | | | | | | | | | | | | | | | | waitxcpt - // | | | | | | | | | | | | | | | | | - List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N),Array( - VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFG,N,Y,Y,N,N,Y,Y,N,N,N,N), - VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N), - VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,N,N,N,N,N,N), - VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_X, Y,Y,N,N,N,N,N,N,N,N,N), - VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,N,N,N,N,N,N), - VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_X, Y,Y,N,N,N,N,N,N,N,N,N), - FENCE_L_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,N), - FENCE_G_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,N), - FENCE_L_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,Y,N), - FENCE_G_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,Y,N), - VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N), - VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N), - VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,Y,N,N,N,N,N), - VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_X, N,N,Y,N,N,N,Y,N,N,N,N), - VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,Y,N,N,N,Y,N,N,N), - VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,Y,N,N,N,Y,N,N), - VWAITXCPT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,Y), - VWAITKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,Y) + // | | | | | | | | vpfcntq + // wen | | | | | | | | | pfq + // val vcmd vimm vimm2 | fn | | | | | | | | | | fence_cv + // | | | | | | | | | | | | | | | | | waitxcpt + // | | | | | | | | | | | | | | | | | | + List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N),Array( + VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFG,N,Y,Y,N,N,Y,Y,N,N,N,N,N), + VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N), + VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,N,N,N,N,N,N,N), + VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_X, Y,Y,N,N,N,N,N,N,N,N,N,N), + VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,N,N,N,N,N,N,N), + VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_X, Y,Y,N,N,N,N,N,N,N,N,N,N), + FENCE_L_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,N,N), + FENCE_G_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,N,N), + FENCE_L_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,Y,N), + FENCE_G_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,Y,N), + VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), + VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), + VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,Y,N,N,N,Y,N,N), + VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_X, N,N,Y,N,N,N,Y,N,N,Y,N,N), + VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,Y,N,N,N,Y,N,Y,N,N), + VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,Y,N,N,N,Y,Y,N,N), + VWAITXCPT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,Y), + VWAITKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,Y) )) val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_sel_vimm2 :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs val wb_vec_cmdq_enq :: wb_vec_ximm1q_enq :: wb_vec_ximm2q_enq :: wb_vec_cntq_enq :: veccs1 = veccs0 val wb_vec_pfcmdq_enq :: wb_vec_pfximm1q_enq :: wb_vec_pfximm2q_enq :: wb_vec_pfcntq_enq :: veccs2 = veccs1 - val wb_vec_fence_cv :: wb_vec_waitxcpt :: Nil = veccs2 + val wb_vec_pfaq :: wb_vec_fence_cv :: wb_vec_waitxcpt :: Nil = veccs2 val valid_common = io.dpath.valid && io.sr_ev && wb_vec_val && !(wb_vec_appvlmask && io.dpath.appvl0) + val wb_vec_pfcmdq_enq_mask_pfq = wb_vec_pfcmdq_enq && (!wb_vec_pfaq || io.dpath.pfq) + val wb_vec_pfximm1q_enq_mask_pfq = wb_vec_pfximm1q_enq && (!wb_vec_pfaq || io.dpath.pfq) + val wb_vec_pfximm2q_enq_mask_pfq = wb_vec_pfximm2q_enq && (!wb_vec_pfaq || io.dpath.pfq) + val wb_vec_pfcntq_enq_mask_pfq = wb_vec_pfcntq_enq && (!wb_vec_pfaq || io.dpath.pfq) + val mask_wb_vec_cmdq_ready = !wb_vec_cmdq_enq || io.iface.vcmdq_ready val mask_wb_vec_ximm1q_ready = !wb_vec_ximm1q_enq || io.iface.vximm1q_ready val mask_wb_vec_ximm2q_ready = !wb_vec_ximm2q_enq || io.iface.vximm2q_ready val mask_wb_vec_cntq_ready = !wb_vec_cntq_enq || io.iface.vcntq_ready - val mask_wb_vec_pfcmdq_ready = !wb_vec_pfcmdq_enq || io.iface.vpfcmdq_ready - val mask_wb_vec_pfximm1q_ready = !wb_vec_pfximm1q_enq || io.iface.vpfximm1q_ready - val mask_wb_vec_pfximm2q_ready = !wb_vec_pfximm2q_enq || io.iface.vpfximm2q_ready - val mask_wb_vec_pfcntq_ready = !wb_vec_pfcntq_enq || io.iface.vpfcntq_ready + val mask_wb_vec_pfcmdq_ready = !wb_vec_pfcmdq_enq_mask_pfq || io.iface.vpfcmdq_ready + val mask_wb_vec_pfximm1q_ready = !wb_vec_pfximm1q_enq_mask_pfq || io.iface.vpfximm1q_ready + val mask_wb_vec_pfximm2q_ready = !wb_vec_pfximm2q_enq_mask_pfq || io.iface.vpfximm2q_ready + val mask_wb_vec_pfcntq_ready = !wb_vec_pfcntq_enq_mask_pfq || io.iface.vpfcntq_ready io.dpath.wen := wb_vec_wen.toBool io.dpath.fn := wb_vec_fn @@ -167,32 +174,32 @@ class rocketCtrlVec extends Component io.iface.vpfcmdq_valid := valid_common && mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && - wb_vec_pfcmdq_enq && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready + wb_vec_pfcmdq_enq_mask_pfq && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready io.iface.vpfximm1q_valid := valid_common && mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && - mask_wb_vec_pfcmdq_ready && wb_vec_pfximm1q_enq && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready + mask_wb_vec_pfcmdq_ready && wb_vec_pfximm1q_enq_mask_pfq && mask_wb_vec_pfximm2q_ready && mask_wb_vec_pfcntq_ready io.iface.vpfximm2q_valid := valid_common && mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && - mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && wb_vec_pfximm2q_enq && mask_wb_vec_pfcntq_ready + mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && wb_vec_pfximm2q_enq_mask_pfq && mask_wb_vec_pfcntq_ready io.iface.vpfcntq_valid := valid_common && mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready && mask_wb_vec_cntq_ready && - mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && wb_vec_pfcntq_enq + mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && mask_wb_vec_pfximm2q_ready && wb_vec_pfcntq_enq_mask_pfq io.replay := valid_common && ( wb_vec_cmdq_enq && !io.iface.vcmdq_ready || wb_vec_ximm1q_enq && !io.iface.vximm1q_ready || wb_vec_ximm2q_enq && !io.iface.vximm2q_ready || wb_vec_cntq_enq && !io.iface.vcntq_ready || - wb_vec_pfcmdq_enq && !io.iface.vpfcmdq_ready || - wb_vec_pfximm1q_enq && !io.iface.vpfximm1q_ready || - wb_vec_pfximm2q_enq && !io.iface.vpfximm2q_ready || - wb_vec_pfcntq_enq && !io.iface.vpfcntq_ready || + wb_vec_pfcmdq_enq_mask_pfq && !io.iface.vpfcmdq_ready || + wb_vec_pfximm1q_enq_mask_pfq && !io.iface.vpfximm1q_ready || + wb_vec_pfximm2q_enq_mask_pfq && !io.iface.vpfximm2q_ready || + wb_vec_pfcntq_enq_mask_pfq && !io.iface.vpfcntq_ready || wb_vec_fence_cv && !io.iface.vfence_ready ) diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 1ef4dd92..7d045fe4 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -145,4 +145,5 @@ class rocketDpathVec extends Component io.ctrl.valid := io.valid io.ctrl.inst := io.inst io.ctrl.appvl0 := reg_appvl0 + io.ctrl.pfq := io.rs2(0) } diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index 4491e80d..5b5a7b89 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -247,10 +247,10 @@ object Instructions val VSETVL = Bits("b?????_?????_000000000000_101_1110011",32); val VF = Bits("b00000_?????_????????????_111_1110011",32); // vector supervisor instructions - val VENQCMD = Bits("b00000_?????_00000_1000000000_1111011",32) - val VENQIMM1 = Bits("b00000_?????_00000_1000000001_1111011",32) - val VENQIMM2 = Bits("b00000_?????_00000_1000000010_1111011",32) - val VENQCNT = Bits("b00000_?????_00000_1000000011_1111011",32) + val VENQCMD = Bits("b00000_?????_?????_1000000000_1111011",32) + val VENQIMM1 = Bits("b00000_?????_?????_1000000001_1111011",32) + val VENQIMM2 = Bits("b00000_?????_?????_1000000010_1111011",32) + val VENQCNT = Bits("b00000_?????_?????_1000000011_1111011",32) val VWAITXCPT = Bits("b00000_00000_00000_1100000000_1111011",32) val VWAITKILL = Bits("b00000_00000_00000_1100000001_1111011",32)