From 44fb3be7d0ed724e7547a2f83bf1204de0294d52 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 28 Mar 2017 16:04:02 -0700 Subject: [PATCH] Fix MMIO/cache refill concurrency bug in DCache There's a structural hazard on s2_req, so disallow cache refill initiation while any MMIO loads are in flight. --- src/main/scala/rocket/DCache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index b8f44c16..a5f4516b 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -167,7 +167,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_valid_hit = s2_valid_masked && s2_readwrite && s2_hit val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_hit && !(pstore1_valid || pstore2_valid) && !release_ack_wait - val s2_valid_cached_miss = s2_valid_miss && !s2_uncached + val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR val s2_victimize = s2_valid_cached_miss || s2_flush_valid val s2_valid_uncached = s2_valid_miss && s2_uncached val s2_victim_way = Mux(s2_hit_valid && !s2_flush_valid, s2_hit_way, UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid)))