From 44ca3b60ab2ba3c425841adc012068d264f9f799 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 20 Mar 2017 01:30:09 -0700
Subject: [PATCH] Retime PTW response valid bits

It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
---
 src/main/scala/rocket/PTW.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala
index 38053af3..b50b61b9 100644
--- a/src/main/scala/rocket/PTW.scala
+++ b/src/main/scala/rocket/PTW.scala
@@ -73,7 +73,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
   val state = Reg(init=s_ready)
   val count = Reg(UInt(width = log2Up(pgLevels)))
   val s1_kill = Reg(next = Bool(false))
-  val resp_valid = Reg(next = Bool(false))
+  val resp_valid = Reg(next = Vec.fill(io.requestor.size)(Bool(false)))
   val exception = Reg(next = io.mem.xcpt.pf.ld)
 
   val r_req = Reg(new PTWReq)
@@ -132,7 +132,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
   io.mem.invalidate_lr := Bool(false)
   
   for (i <- 0 until io.requestor.size) {
-    io.requestor(i).resp.valid := resp_valid && (r_req_dest === i)
+    io.requestor(i).resp.valid := resp_valid(i)
     io.requestor(i).resp.bits.pte := r_pte
     io.requestor(i).resp.bits.level := count
     io.requestor(i).resp.bits.pte.ppn := pte_addr >> pgIdxBits
@@ -172,13 +172,13 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
           count := count + 1
         }.otherwise {
           state := s_ready
-          resp_valid := true
+          resp_valid(r_req_dest) := true
         }
       }
       when (exception) {
         r_pte.v := false
         state := s_ready
-        resp_valid := true
+        resp_valid(r_req_dest) := true
       }
     }
   }