riscv/rocket-chip
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parameterize Hasti address and data bits

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Howard Mao committed 2016-05-06 11:30:50 -07:00
1 parent 64991d3947
commit 44740cb6b2
1 file changed
+6 -2
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junctions/src/main/scala/hasti.scala
+6 -2
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@@ -31,10 +31,14 @@ trait HastiConstants
def dgate(valid: Bool, b: UInt) = Fill(b.getWidth, valid) & b def dgate(valid: Bool, b: UInt) = Fill(b.getWidth, valid) & b
} }
case class HastiParameters(dataBits: Int, addrBits: Int)
case object HastiKey extends Field[HastiParameters]
trait HasHastiParameters { trait HasHastiParameters {
implicit val p: Parameters implicit val p: Parameters
val hastiAddrBits = 32 val hastiParams = p(HastiKey)
val hastiDataBits = 32 val hastiAddrBits = hastiParams.addrBits
val hastiDataBits = hastiParams.dataBits
} }
abstract class HastiModule(implicit val p: Parameters) extends Module abstract class HastiModule(implicit val p: Parameters) extends Module