From ed091f55e694275c9d1d18b819a5a6b2a5b00e69 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 15 Dec 2016 12:10:04 -0800 Subject: [PATCH 1/3] apb: diplomatic APB framework --- src/main/scala/uncore/apb/Bundles.scala | 32 +++++++ src/main/scala/uncore/apb/Nodes.scala | 59 ++++++++++++ src/main/scala/uncore/apb/Parameters.scala | 86 +++++++++++++++++ src/main/scala/uncore/apb/Protocol.scala | 16 ++++ .../scala/uncore/apb/RegisterRouter.scala | 96 +++++++++++++++++++ src/main/scala/uncore/apb/SRAM.scala | 48 ++++++++++ src/main/scala/uncore/apb/Test.scala | 40 ++++++++ src/main/scala/uncore/apb/Xbar.scala | 49 ++++++++++ src/main/scala/uncore/apb/package.scala | 11 +++ 9 files changed, 437 insertions(+) create mode 100644 src/main/scala/uncore/apb/Bundles.scala create mode 100644 src/main/scala/uncore/apb/Nodes.scala create mode 100644 src/main/scala/uncore/apb/Parameters.scala create mode 100644 src/main/scala/uncore/apb/Protocol.scala create mode 100644 src/main/scala/uncore/apb/RegisterRouter.scala create mode 100644 src/main/scala/uncore/apb/SRAM.scala create mode 100644 src/main/scala/uncore/apb/Test.scala create mode 100644 src/main/scala/uncore/apb/Xbar.scala create mode 100644 src/main/scala/uncore/apb/package.scala diff --git a/src/main/scala/uncore/apb/Bundles.scala b/src/main/scala/uncore/apb/Bundles.scala new file mode 100644 index 00000000..da40ce67 --- /dev/null +++ b/src/main/scala/uncore/apb/Bundles.scala @@ -0,0 +1,32 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ +import util.GenericParameterizedBundle + +abstract class APBBundleBase(params: APBBundleParameters) extends GenericParameterizedBundle(params) + +// Signal directions are from the master's point-of-view +class APBBundle(params: APBBundleParameters) extends APBBundleBase(params) +{ + // Flow control signals from the master + val psel = Bool(OUTPUT) + val penable = Bool(OUTPUT) + + // Payload signals + val pwrite = Bool(OUTPUT) + val paddr = UInt(OUTPUT, width = params.addrBits) + val pprot = UInt(OUTPUT, width = params.protBits) + val pwdata = UInt(OUTPUT, width = params.dataBits) + val pstrb = UInt(OUTPUT, width = params.dataBits/8) + + val pready = Bool(INPUT) + val pslverr = Bool(INPUT) + val prdata = UInt(INPUT, width = params.dataBits) +} + +object APBBundle +{ + def apply(params: APBBundleParameters) = new APBBundle(params) +} diff --git a/src/main/scala/uncore/apb/Nodes.scala b/src/main/scala/uncore/apb/Nodes.scala new file mode 100644 index 00000000..0663875b --- /dev/null +++ b/src/main/scala/uncore/apb/Nodes.scala @@ -0,0 +1,59 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ +import chisel3.internal.sourceinfo.SourceInfo +import config._ +import diplomacy._ + +object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBEdgeParameters, APBBundle] +{ + def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu) + def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu) + def bundleO(eo: Seq[APBEdgeParameters]): Vec[APBBundle] = { + require (!eo.isEmpty) + Vec(eo.size, APBBundle(eo.map(_.bundle).reduce(_.union(_)))) + } + def bundleI(ei: Seq[APBEdgeParameters]): Vec[APBBundle] = { + require (!ei.isEmpty) + Vec(ei.size, APBBundle(ei.map(_.bundle).reduce(_.union(_)))) + } + + def colour = "#00ccff" // bluish + override def labelI(ei: APBEdgeParameters) = (ei.slave.beatBytes * 8).toString + override def labelO(eo: APBEdgeParameters) = (eo.slave.beatBytes * 8).toString + + def connect(bo: => APBBundle, bi: => APBBundle, ei: => APBEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { + (None, () => { bi <> bo }) + } + + override def mixO(pd: APBMasterPortParameters, node: OutwardNode[APBMasterPortParameters, APBSlavePortParameters, APBBundle]): APBMasterPortParameters = + pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) + override def mixI(pu: APBSlavePortParameters, node: InwardNode[APBMasterPortParameters, APBSlavePortParameters, APBBundle]): APBSlavePortParameters = + pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) }) +} + +// Nodes implemented inside modules +case class APBIdentityNode() extends IdentityNode(APBImp) +case class APBMasterNode(portParams: APBMasterPortParameters, numPorts: Range.Inclusive = 1 to 1) + extends SourceNode(APBImp)(portParams, numPorts) +case class APBSlaveNode(portParams: APBSlavePortParameters, numPorts: Range.Inclusive = 1 to 1) + extends SinkNode(APBImp)(portParams, numPorts) +case class APBAdapterNode( + masterFn: Seq[APBMasterPortParameters] => APBMasterPortParameters, + slaveFn: Seq[APBSlavePortParameters] => APBSlavePortParameters, + numMasterPorts: Range.Inclusive = 1 to 1, + numSlavePorts: Range.Inclusive = 1 to 1) + extends InteriorNode(APBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts) + +// Nodes passed from an inner module +case class APBOutputNode() extends OutputNode(APBImp) +case class APBInputNode() extends InputNode(APBImp) + +// Nodes used for external ports +case class APBBlindOutputNode(portParams: APBSlavePortParameters) extends BlindOutputNode(APBImp)(portParams) +case class APBBlindInputNode(portParams: APBMasterPortParameters) extends BlindInputNode(APBImp)(portParams) + +case class APBInternalOutputNode(portParams: APBSlavePortParameters) extends InternalOutputNode(APBImp)(portParams) +case class APBInternalInputNode(portParams: APBMasterPortParameters) extends InternalInputNode(APBImp)(portParams) diff --git a/src/main/scala/uncore/apb/Parameters.scala b/src/main/scala/uncore/apb/Parameters.scala new file mode 100644 index 00000000..dd75c7e2 --- /dev/null +++ b/src/main/scala/uncore/apb/Parameters.scala @@ -0,0 +1,86 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ +import config._ +import diplomacy._ +import scala.math.max + +case class APBSlaveParameters( + address: Seq[AddressSet], + regionType: RegionType.T = RegionType.GET_EFFECTS, + executable: Boolean = false, // processor can execute from this memory + nodePath: Seq[BaseNode] = Seq(), + supportsWrite: Boolean = true, + supportsRead: Boolean = true) +{ + address.foreach { a => require (a.finite) } + address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) } + + val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") + val maxAddress = address.map(_.max).max + val minAlignment = address.map(_.alignment).min +} + +case class APBSlavePortParameters( + slaves: Seq[APBSlaveParameters], + beatBytes: Int) +{ + require (!slaves.isEmpty) + require (isPow2(beatBytes)) + + val maxAddress = slaves.map(_.maxAddress).max + + lazy val routingMask = AddressDecoder(slaves.map(_.address)) + def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _))) + def findFast(address: UInt) = Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) + + // Require disjoint ranges for addresses + slaves.combinations(2).foreach { case Seq(x,y) => + x.address.foreach { a => y.address.foreach { b => + require (!a.overlaps(b)) + } } + } +} + +case class APBMasterParameters( + nodePath: Seq[BaseNode] = Seq()) +{ + val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") +} + +case class APBMasterPortParameters( + masters: Seq[APBMasterParameters]) + +case class APBBundleParameters( + addrBits: Int, + dataBits: Int) +{ + require (dataBits >= 8) + require (addrBits >= 1) + require (isPow2(dataBits)) + + // Bring the globals into scope + val protBits = APBParameters.protBits + + def union(x: APBBundleParameters) = + APBBundleParameters( + max(addrBits, x.addrBits), + max(dataBits, x.dataBits)) +} + +object APBBundleParameters +{ + def apply(master: APBMasterPortParameters, slave: APBSlavePortParameters) = + new APBBundleParameters( + addrBits = log2Up(slave.maxAddress+1), + dataBits = slave.beatBytes * 8) +} + +case class APBEdgeParameters( + master: APBMasterPortParameters, + slave: APBSlavePortParameters) +{ + val bundle = APBBundleParameters(master, slave) +} diff --git a/src/main/scala/uncore/apb/Protocol.scala b/src/main/scala/uncore/apb/Protocol.scala new file mode 100644 index 00000000..b7c3c333 --- /dev/null +++ b/src/main/scala/uncore/apb/Protocol.scala @@ -0,0 +1,16 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ + +object APBParameters +{ + // These are all fixed by the AHB standard: + val protBits = 3 + + val PROT_PRIVILEDGED = UInt(1, width = protBits) + val PROT_NONSECURE = UInt(2, width = protBits) + val PROT_INSTRUCTION = UInt(4, width = protBits) + def PROT_DEFAULT = PROT_PRIVILEDGED +} diff --git a/src/main/scala/uncore/apb/RegisterRouter.scala b/src/main/scala/uncore/apb/RegisterRouter.scala new file mode 100644 index 00000000..20bf4928 --- /dev/null +++ b/src/main/scala/uncore/apb/RegisterRouter.scala @@ -0,0 +1,96 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ +import config._ +import diplomacy._ +import regmapper._ +import scala.math.{min,max} + +class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) + extends APBSlaveNode(APBSlavePortParameters( + Seq(APBSlaveParameters( + address = Seq(address), + executable = executable, + supportsWrite = true, + supportsRead = true)), + beatBytes = beatBytes)) +{ + require (address.contiguous) + + // Calling this method causes the matching APB bundle to be + // configured to route all requests to the listed RegFields. + def regmap(mapping: RegField.Map*) = { + val apb = bundleIn(0) + + val indexBits = log2Up((address.mask+1)/beatBytes) + val params = RegMapperParams(indexBits, beatBytes, 1) + val in = Wire(Decoupled(new RegMapperInput(params))) + val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) + + // Only send the request to the RR once + val taken = RegInit(Bool(false)) + when (in.fire()) { taken := Bool(true) } + when (out.fire()) { taken := Bool(false) } + + in.bits.read := !apb.pwrite + in.bits.index := apb.paddr >> log2Ceil(beatBytes) + in.bits.data := apb.pwdata + in.bits.mask := Mux(apb.pwrite, apb.pstrb, UInt((1< B, router: APBRegisterRouterBase) + extends LazyModuleImp(router) with HasRegMap +{ + val io = bundleBuilder + val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0) + def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) +} + +class APBRegisterRouter[B <: APBRegBundleBase, M <: LazyModuleImp] + (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) + (bundleBuilder: APBRegBundleArg => B) + (moduleBuilder: (=> B, APBRegisterRouterBase) => M)(implicit p: Parameters) + extends APBRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable) +{ + require (isPow2(size)) + // require (size >= 4096) ... not absolutely required, but highly recommended + + lazy val module = moduleBuilder(bundleBuilder(APBRegBundleArg(intnode.bundleOut, node.bundleIn)), this) +} diff --git a/src/main/scala/uncore/apb/SRAM.scala b/src/main/scala/uncore/apb/SRAM.scala new file mode 100644 index 00000000..c2bf6d1f --- /dev/null +++ b/src/main/scala/uncore/apb/SRAM.scala @@ -0,0 +1,48 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ +import config._ +import diplomacy._ + +class APBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule +{ + val node = APBSlaveNode(APBSlavePortParameters( + Seq(APBSlaveParameters( + address = List(address), + regionType = RegionType.UNCACHED, + executable = executable, + supportsRead = true, + supportsWrite = true)), + beatBytes = beatBytes)) + + // We require the address range to include an entire beat (for the write mask) + require ((address.mask & (beatBytes-1)) == beatBytes-1) + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = node.bundleIn + } + + val in = io.in(0) + + def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] = + if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail) + val mask = bigBits(address.mask >> log2Ceil(beatBytes)) + val paddr = Cat((mask zip (in.paddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse) + + // Use single-ported memory with byte-write enable + val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8))) + def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in) + + val read = in.psel && !in.penable && !in.pwrite + when (in.psel && !in.penable && in.pwrite) { + mem.write(paddr, Vec.tabulate(beatBytes) { i => in.pwdata(8*(i+1)-1, 8*i) }, in.pstrb.toBools) + } + + in.pready := Bool(true) + in.pslverr := Bool(false) + in.prdata := holdUnless(mem.read(paddr, read).asUInt, RegNext(read)) + } +} diff --git a/src/main/scala/uncore/apb/Test.scala b/src/main/scala/uncore/apb/Test.scala new file mode 100644 index 00000000..2163b5cb --- /dev/null +++ b/src/main/scala/uncore/apb/Test.scala @@ -0,0 +1,40 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ +import config._ +import diplomacy._ +import uncore.tilelink2._ +import unittest._ + +class RRTest0(address: BigInt)(implicit p: Parameters) extends APBRegisterRouter(address, 0, 32, 0, 4)( + new APBRegBundle((), _) with RRTest0Bundle)( + new APBRegModule((), _, _) with RRTest0Module) + +class RRTest1(address: BigInt)(implicit p: Parameters) extends APBRegisterRouter(address, 0, 32, 1, 4, false)( + new APBRegBundle((), _) with RRTest1Bundle)( + new APBRegModule((), _, _) with RRTest1Module) + +class APBFuzzBridge()(implicit p: Parameters) extends LazyModule +{ + val fuzz = LazyModule(new TLFuzzer(5000)) + val model = LazyModule(new TLRAMModel("APBFuzzMaster")) + var xbar = LazyModule(new APBFanout) + val ram = LazyModule(new APBRAM(AddressSet(0x0, 0xff))) + val gpio = LazyModule(new RRTest0(0x100)) + + model.node := fuzz.node +// xbar.node := TLToAPB()(model.node) + ram.node := xbar.node + gpio.node := xbar.node + + lazy val module = new LazyModuleImp(this) with HasUnitTestIO { + io.finished := fuzz.module.io.finished + } +} + +class APBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) { + val dut = Module(LazyModule(new APBFuzzBridge).module) + io.finished := dut.io.finished +} diff --git a/src/main/scala/uncore/apb/Xbar.scala b/src/main/scala/uncore/apb/Xbar.scala new file mode 100644 index 00000000..2809fb96 --- /dev/null +++ b/src/main/scala/uncore/apb/Xbar.scala @@ -0,0 +1,49 @@ +// See LICENSE.SiFive for license details. + +package uncore.apb + +import Chisel._ +import config._ +import diplomacy._ +import regmapper._ +import scala.math.{min,max} + +class APBFanout()(implicit p: Parameters) extends LazyModule { + val node = APBAdapterNode( + numSlavePorts = 1 to 1, + numMasterPorts = 1 to 32, + masterFn = { case Seq(m) => m }, + slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) }) + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = node.bundleIn + val out = node.bundleOut + } + + val in = io.in(0) + + // Require consistent bus widths + val port0 = node.edgesOut(0).slave + node.edgesOut.foreach { edge => + val port = edge.slave + require (port.beatBytes == port0.beatBytes, + s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}") + } + + val port_addrs = node.edgesOut.map(_.slave.slaves.map(_.address).flatten) + val routingMask = AddressDecoder(port_addrs) + val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct) + + val sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.paddr)).reduce(_ || _))) + (sel zip io.out) foreach { case (sel, out) => + out := in + out.psel := sel && in.psel + out.penable := sel && in.penable + } + + in.pready := !Mux1H(sel, io.out.map(!_.pready)) + in.pslverr := Mux1H(sel, io.out.map(_.pslverr)) + in.prdata := Mux1H(sel, io.out.map(_.prdata)) + } +} diff --git a/src/main/scala/uncore/apb/package.scala b/src/main/scala/uncore/apb/package.scala new file mode 100644 index 00000000..d6f9bd4d --- /dev/null +++ b/src/main/scala/uncore/apb/package.scala @@ -0,0 +1,11 @@ +// See LICENSE.SiFive for license details. + +package uncore + +import Chisel._ +import diplomacy._ + +package object apb +{ + type APBOutwardNode = OutwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle] +} From 16febe7e949ea8c89cab395c730644d5ec00ac5a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 15 Dec 2016 14:16:01 -0800 Subject: [PATCH 2/3] apb: add a TileLink to APB bridge and unittest it --- src/main/scala/uncore/apb/Test.scala | 2 +- src/main/scala/uncore/tilelink2/ToAPB.scala | 101 ++++++++++++++++++++ src/main/scala/unittest/Configs.scala | 1 + 3 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 src/main/scala/uncore/tilelink2/ToAPB.scala diff --git a/src/main/scala/uncore/apb/Test.scala b/src/main/scala/uncore/apb/Test.scala index 2163b5cb..960fd73d 100644 --- a/src/main/scala/uncore/apb/Test.scala +++ b/src/main/scala/uncore/apb/Test.scala @@ -25,7 +25,7 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule val gpio = LazyModule(new RRTest0(0x100)) model.node := fuzz.node -// xbar.node := TLToAPB()(model.node) + xbar.node := TLToAPB()(model.node) ram.node := xbar.node gpio.node := xbar.node diff --git a/src/main/scala/uncore/tilelink2/ToAPB.scala b/src/main/scala/uncore/tilelink2/ToAPB.scala new file mode 100644 index 00000000..218892f6 --- /dev/null +++ b/src/main/scala/uncore/tilelink2/ToAPB.scala @@ -0,0 +1,101 @@ +// See LICENSE.SiFive for license details. + +package uncore.tilelink2 + +import Chisel._ +import chisel3.internal.sourceinfo.SourceInfo +import config._ +import diplomacy._ +import uncore.apb._ +import scala.math.{min, max} +import APBParameters._ + +case class TLToAPBNode() extends MixedNode(TLImp, APBImp)( + dFn = { case (1, Seq(TLClientPortParameters(clients, unsafeAtomics, minLatency))) => + val masters = clients.map { case c => APBMasterParameters(nodePath = c.nodePath) } + Seq(APBMasterPortParameters(masters)) + }, + uFn = { case (1, Seq(APBSlavePortParameters(slaves, beatBytes))) => + val managers = slaves.map { case s => + TLManagerParameters( + address = s.address, + regionType = s.regionType, + executable = s.executable, + nodePath = s.nodePath, + supportsGet = if (s.supportsRead) TransferSizes(1, beatBytes) else TransferSizes.none, + supportsPutPartial = if (s.supportsWrite) TransferSizes(1, beatBytes) else TransferSizes.none, + supportsPutFull = if (s.supportsWrite) TransferSizes(1, beatBytes) else TransferSizes.none, + fifoId = Some(0)) // a common FIFO domain + } + Seq(TLManagerPortParameters(managers, beatBytes, 1, 0)) + }, + numPO = 1 to 1, + numPI = 1 to 1) + +class TLToAPB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule +{ + val node = TLToAPBNode() + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = node.bundleIn + val out = node.bundleOut + } + + val in = io.in(0) + val out = io.out(0) + val edgeIn = node.edgesIn(0) + val edgeOut = node.edgesOut(0) + val beatBytes = edgeOut.slave.beatBytes + val lgBytes = log2Ceil(beatBytes) + + // APB has no cache coherence + in.b.valid := Bool(false) + in.c.ready := Bool(true) + in.e.ready := Bool(true) + + // We need a skidpad to capture D output: + // We cannot know if the D response will be accepted until we have + // presented it on D as valid. We also can't back-pressure APB in the + // data phase. Therefore, we must have enough space to save the data + // phase result. Whenever we have a queued response, we can not allow + // APB to present new responses, so we must quash the address phase. + val d = Wire(in.d) + in.d <> Queue(d, 1, flow = true) + + // We need an irrevocable input for APB to stall + val a = Queue(in.a, 1, flow = combinational, pipe = !combinational) + + val a_enable = RegInit(Bool(false)) + val a_sel = a.valid && RegNext(!in.d.valid || in.d.ready) + val a_write = edgeIn.hasData(a.bits) + + when (a_sel) { a_enable := Bool(true) } + when (d.fire()) { a_enable := Bool(false) } + + out.psel := a_sel + out.penable := a_enable + out.pwrite := a_write + out.paddr := a.bits.address + out.pprot := PROT_DEFAULT + out.pwdata := a.bits.data + out.pstrb := Mux(a_write, a.bits.mask, UInt(0)) + + a.ready := a_enable && out.pready + d.valid := a_enable && out.pready + assert (!d.valid || d.ready) + + d.bits := edgeIn.AccessAck(a.bits, UInt(0), out.prdata, out.pslverr) + d.bits.opcode := Mux(a_write, TLMessages.AccessAck, TLMessages.AccessAckData) + } +} + +object TLToAPB +{ + // applied to the TL source node; y.node := TLToAPB()(x.node) + def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): APBOutwardNode = { + val apb = LazyModule(new TLToAPB(combinational)) + apb.node := x + apb.node + } +} diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index ab714be3..62efd91a 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -33,6 +33,7 @@ class WithUncoreUnitTests extends Config( Module(new uncore.converters.TileLinkWidthAdapterTest()), Module(new uncore.tilelink2.TLFuzzRAMTest), Module(new uncore.ahb.AHBBridgeTest), + Module(new uncore.apb.APBBridgeTest), Module(new uncore.axi4.AXI4LiteFuzzRAMTest), Module(new uncore.axi4.AXI4FullFuzzRAMTest), Module(new uncore.axi4.AXI4BridgeTest)) } From a9b264e5821ab90c04207ad3aeff7576e42e8f0b Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 15 Dec 2016 14:24:39 -0800 Subject: [PATCH 3/3] ahb: lower hsel when idle to save power --- src/main/scala/uncore/ahb/Bundles.scala | 2 +- src/main/scala/uncore/ahb/Protocol.scala | 1 - src/main/scala/uncore/ahb/Xbar.scala | 2 +- src/main/scala/uncore/tilelink2/ToAHB.scala | 9 ++++----- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/src/main/scala/uncore/ahb/Bundles.scala b/src/main/scala/uncore/ahb/Bundles.scala index 5822ff74..caf6d307 100644 --- a/src/main/scala/uncore/ahb/Bundles.scala +++ b/src/main/scala/uncore/ahb/Bundles.scala @@ -13,7 +13,7 @@ class AHBBundle(params: AHBBundleParameters) extends AHBBundleBase(params) // Flow control signals from the master val hmastlock = Bool(OUTPUT) val htrans = UInt(OUTPUT, width = params.transBits) - val hsel = Bool(OUTPUT) // on a master, drive this with true + val hsel = Bool(OUTPUT) val hready = Bool(OUTPUT) // on a master, drive this from readyout // Payload signals diff --git a/src/main/scala/uncore/ahb/Protocol.scala b/src/main/scala/uncore/ahb/Protocol.scala index 4dbd9f78..ba7c6b28 100644 --- a/src/main/scala/uncore/ahb/Protocol.scala +++ b/src/main/scala/uncore/ahb/Protocol.scala @@ -3,7 +3,6 @@ package uncore.ahb import Chisel._ -import chisel3.util.{Irrevocable, IrrevocableIO} object AHBParameters { diff --git a/src/main/scala/uncore/ahb/Xbar.scala b/src/main/scala/uncore/ahb/Xbar.scala index 41ccf55f..e3128a6d 100644 --- a/src/main/scala/uncore/ahb/Xbar.scala +++ b/src/main/scala/uncore/ahb/Xbar.scala @@ -22,7 +22,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule { } // Require consistent bus widths - val port0 = node.edgesIn(0).slave + val port0 = node.edgesOut(0).slave node.edgesOut.foreach { edge => val port = edge.slave require (port.beatBytes == port0.beatBytes, diff --git a/src/main/scala/uncore/tilelink2/ToAHB.scala b/src/main/scala/uncore/tilelink2/ToAHB.scala index bdc8b454..7ceb86f7 100644 --- a/src/main/scala/uncore/tilelink2/ToAHB.scala +++ b/src/main/scala/uncore/tilelink2/ToAHB.scala @@ -6,7 +6,6 @@ import Chisel._ import chisel3.internal.sourceinfo.SourceInfo import config._ import diplomacy._ -import util.PositionalMultiQueue import uncore.ahb._ import scala.math.{min, max} import AHBParameters._ @@ -119,7 +118,7 @@ class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends Laz out.hmastlock := Bool(false) // for now out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY)) - out.hsel := Bool(true) + out.hsel := a_valid || !a_first out.hready := out.hreadyout out.hwrite := a_hasData out.haddr := a.bits.address | a_offset @@ -134,8 +133,8 @@ object TLToAHB { // applied to the TL source node; y.node := TLToAHB()(x.node) def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = { - val axi4 = LazyModule(new TLToAHB(combinational)) - axi4.node := x - axi4.node + val ahb = LazyModule(new TLToAHB(combinational)) + ahb.node := x + ahb.node } }