riscv/rocket-chip
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dcache fixes - all tests and ubmarks pass, hello world still broken

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Rimas Avizienis
2011-11-04 15:40:41 -07:00
parent 3a02028a35
commit 4459935554
5 changed files with 109 additions and 75 deletions
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4
rocket/src/main/scala/cpu.scala
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@ -8,6 +8,10 @@ class ioDebug extends Bundle()
{
val error_mode = Bool('output);
val log_control = Bool('output);
val id_valid = Bool('output);
val ex_valid = Bool('output);
val mem_valid = Bool('output);
val wb_valid = Bool('output);
}
class ioHost(view: List[String] = null) extends Bundle(view)