riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

crossings: change defaults to sync=3 for safer settling time

Browse Source 
Make the matching AsyncQueue depth=8 to support full throughput
This commit is contained in:
Wesley W. Terpstra
2016-09-13 15:49:08 -07:00
parent 3348236320
commit 44501cdbf8
2 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/uncore/devices/Debug.scala
View File

@ -994,7 +994,7 @@ object AsyncDebugBusCrossing {
object AsyncDebugBusFrom { // OutsideClockDomain
// takes from_source from the 'from' clock domain and puts it into your clock domain
def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, depth: Int = 0, sync: Int = 2): DebugBusIO = {
def apply(from_clock: Clock, from_reset: Bool, from_source: DebugBusIO, depth: Int = 1, sync: Int = 3): DebugBusIO = {
val scope = AsyncScope()
AsyncDebugBusCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
}
@ -1002,7 +1002,7 @@ object AsyncDebugBusFrom { // OutsideClockDomain
object AsyncDebugBusTo { // OutsideClockDomain
// takes source from your clock domain and puts it into the 'to' clock domain
def apply(to_clock: Clock, to_reset: Bool, source: DebugBusIO, depth: Int = 0, sync: Int = 2): DebugBusIO = {
def apply(to_clock: Clock, to_reset: Bool, source: DebugBusIO, depth: Int = 1, sync: Int = 3): DebugBusIO = {
val scope = AsyncScope()
AsyncDebugBusCrossing(scope.clock, scope.reset, source, to_clock, to_reset, depth, sync)
}