riscv/rocket-chip
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Debug regressions: Add necessary config scripts

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This commit is contained in:
Megan Wachs 2017-11-03 08:26:03 -07:00
parent e82328336e
commit 4449dd0baa
4 changed files with 71 additions and 5 deletions
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8
regression/Makefile
View File

@ -228,7 +228,7 @@ stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(VSIM_JTAG_VCDPLUS_32)" \
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
$(abspath $(TOP))/scripts/FreedomSim.py \
$(abspath $(TOP))/scripts/RocketSim.py \
$(JTAG_DTM_TEST)
date > $@
@ -237,7 +237,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
--sim_cmdrun "$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(VSIM_JTAG_VCDPLUS_64)" \
--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
$(abspath $(TOP))/scripts/FreedomSim.py \
$(abspath $(TOP))/scripts/RocketSim.py \
$(JTAG_DTM_TEST)
date > $@
@ -246,7 +246,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
--sim_cmd "$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(EMULATOR_JTAG_VCDPLUS_32) dummybin | tee emulator.log" \
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
$(abspath $(TOP))/scripts/FreedomSim.py \
$(abspath $(TOP))/scripts/RocketSim.py \
$(JTAG_DTM_TEST)
date > $@
@ -255,7 +255,7 @@ stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
--sim_cmd "$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(EMULATOR_JTAG_VCDPLUS_64) dummybin | tee emulator.log" \
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
$(abspath $(TOP))/scripts/FreedomSim.py \
$(abspath $(TOP))/scripts/RocketSim.py \
$(JTAG_DTM_TEST)
date > $@

19
scripts/RocketSim.cfg Normal file
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@ -0,0 +1,19 @@
adapter_khz 10000
interface remote_bitbang
remote_bitbang_host localhost
#$::env(REMOTE_BITBANG_HOST)
remote_bitbang_port $::env(JTAG_VPI_PORT)
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120
init
halt
echo "Ready for Remote Connections"

16
scripts/RocketSim.py Normal file
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@ -0,0 +1,16 @@
import targets
import testlib
class RocketSimHart(targets.Hart):
pass
class RocketSim(targets.Target):
harts = [RocketSimHart()]
timeout_sec = 6000
server_timeout_sec = 60*60
openocd_config_path = "RocketSim.cfg"
def create(self):
print "STARTING A SIMULATION"
print self.sim_cmd
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)

33
src/main/scala/devices/debug/Periphery.scala
View File

@ -49,7 +49,8 @@ trait HasPeripheryDebugBundle {
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
debug.systemjtag.foreach { sj =>
val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
//val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, sj.reset, c, r, out)
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
}
debug.psd.foreach { _ <> psd }
@ -112,6 +113,36 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
}
}
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) {
val io = new Bundle {
val clock = Clock(INPUT)
val reset = Bool(INPUT)
val jtag = new JTAGIO(hasTRSTn = true)
val enable = Bool(INPUT)
val init_done = Bool(INPUT)
val exit = UInt(OUTPUT, 32)
}
def connect(dutio: JTAGIO, jtag_reset: Bool, tbclock: Clock, tbreset: Bool, tbsuccess: Bool) = {
dutio <> io.jtag
jtag_reset := tbreset
io.clock := tbclock
io.reset := tbreset
io.enable := ~tbreset
io.init_done := ~tbreset
// Success is determined by the gdbserver
// which is controlling this simulation.
tbsuccess := io.exit === UInt(1)
when (io.exit >= UInt(2)) {
printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
stop(1)
}
}
}
class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Parameters)
extends BlackBox ( Map ("TCK_HALF_PERIOD" -> IntParam(tckHalfPeriod),
"CMD_DELAY" -> IntParam(cmdDelay))) {