riscv/rocket-chip
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Debug regressions: Add necessary config scripts

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This commit is contained in:
Megan Wachs
2017-11-03 08:26:03 -07:00
parent e82328336e
commit 4449dd0baa
4 changed files with 71 additions and 5 deletions
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33
src/main/scala/devices/debug/Periphery.scala
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@ -49,7 +49,8 @@ trait HasPeripheryDebugBundle {
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
debug.systemjtag.foreach { sj =>
val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
//val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, sj.reset, c, r, out)
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
}
debug.psd.foreach { _ <> psd }
@ -112,6 +113,36 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
}
}
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) {
val io = new Bundle {
val clock = Clock(INPUT)
val reset = Bool(INPUT)
val jtag = new JTAGIO(hasTRSTn = true)
val enable = Bool(INPUT)
val init_done = Bool(INPUT)
val exit = UInt(OUTPUT, 32)
}
def connect(dutio: JTAGIO, jtag_reset: Bool, tbclock: Clock, tbreset: Bool, tbsuccess: Bool) = {
dutio <> io.jtag
jtag_reset := tbreset
io.clock := tbclock
io.reset := tbreset
io.enable := ~tbreset
io.init_done := ~tbreset
// Success is determined by the gdbserver
// which is controlling this simulation.
tbsuccess := io.exit === UInt(1)
when (io.exit >= UInt(2)) {
printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
stop(1)
}
}
}
class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Parameters)
extends BlackBox ( Map ("TCK_HALF_PERIOD" -> IntParam(tckHalfPeriod),
"CMD_DELAY" -> IntParam(cmdDelay))) {