riscv/rocket-chip
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dcache: we need the bits within the beat so select the right word (#575)

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We now have confirmation that it fixed the problem.
This commit is contained in:
Wesley W. Terpstra 2017-03-08 00:19:09 -08:00 committed by GitHub
parent 603b8af2eb
commit 43dea38ee9
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -307,7 +307,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
s2_req.cmd := req.cmd s2_req.cmd := req.cmd
s2_req.typ := req.typ s2_req.typ := req.typ
s2_req.tag := req.tag s2_req.tag := req.tag
s2_req.addr := Cat(s1_paddr >> wordOffBits /* don't-care */, req.addr(wordOffBits-1, 0)) s2_req.addr := Cat(s1_paddr >> beatOffBits /* don't-care */, req.addr(beatOffBits-1, 0))
} .elsewhen (grantIsVoluntary) { } .elsewhen (grantIsVoluntary) {
assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle!
release_ack_wait := false release_ack_wait := false