riscv/rocket-chip
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fix remaining vsim harness typo

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This commit is contained in:
Howard Mao 2015-10-19 20:20:14 -07:00
parent 896aa892d1
commit 4346111d2a
1 changed files with 1 additions and 1 deletions
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vsrc/rocketTestHarness.v
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@ -125,7 +125,7 @@ module rocketTestHarness;
`ifndef FPGA `ifndef FPGA
.io_host_clk(htif_clk), .io_host_clk(htif_clk),
.io_host_clk_edge(), .io_host_clk_edge(),
.io_host_debug_stats_pcr(htif_out_stats_delay), .io_host_debug_stats_csr(htif_out_stats_delay),
`ifdef MEM_BACKUP_EN `ifdef MEM_BACKUP_EN
.io_mem_backup_ctrl_en(1'b1), .io_mem_backup_ctrl_en(1'b1),