Merge pull request #910 from freechipsproject/tilelink-map

Tilelink map

src/main/scala/coreplex/MemoryBus.scala

@@ -68,7 +68,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
     for (bank <- 0 until nBanksPerChannel) {
       val offset = (bank * nMemoryChannels) + channel
       in := sbus.toMemoryBus
-      mbus.fromCoherenceManager := TLFilter(AddressSet(offset * blockBytes, mask))(out)
+      mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * blockBytes, mask)))(out)
     }
     mbus
   }

src/main/scala/tilelink/Filter.scala

@@ -8,12 +8,60 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
 
-class TLFilter(select: AddressSet)(implicit p: Parameters) extends LazyModule
+class TLFilter(
+  Mfilter: TLManagerParameters => Option[TLManagerParameters] = TLFilter.Midentity,
+  Cfilter: TLClientParameters  => Option[TLClientParameters]  = TLFilter.Cidentity
+  )(implicit p: Parameters) extends LazyModule
 {
   val node = TLAdapterNode(
-    clientFn  = { cp => cp },
+    clientFn  = { cp => cp.copy(clients = cp.clients.flatMap { c =>
-    managerFn = { mp =>
+      val out = Cfilter(c)
-      mp.copy(managers = mp.managers.map { m =>
+      out.map { o => // Confirm the filter only REMOVES capability
+        require (c.sourceId.contains(o.sourceId))
+        require (c.supportsProbe.contains(o.supportsProbe))
+        require (c.supportsArithmetic.contains(o.supportsArithmetic))
+        require (c.supportsLogical.contains(o.supportsLogical))
+        require (c.supportsGet.contains(o.supportsGet))
+        require (c.supportsPutFull.contains(o.supportsPutFull))
+        require (c.supportsPutPartial.contains(o.supportsPutPartial))
+        require (c.supportsHint.contains(o.supportsHint))
+        require (!c.requestFifo || o.requestFifo)
+      }
+      out
+    })},
+    managerFn = { mp => mp.copy(managers = mp.managers.flatMap { m =>
+      val out = Mfilter(m)
+      out.map { o => // Confirm the filter only REMOVES capability
+        o.address.foreach { a => require (m.address.map(_.contains(a)).reduce(_||_)) }
+        require (o.regionType <= m.regionType)
+        // we allow executable to be changed both ways
+        require (m.supportsAcquireT.contains(o.supportsAcquireT))
+        require (m.supportsAcquireB.contains(o.supportsAcquireB))
+        require (m.supportsArithmetic.contains(o.supportsArithmetic))
+        require (m.supportsLogical.contains(o.supportsLogical))
+        require (m.supportsGet.contains(o.supportsGet))
+        require (m.supportsPutFull.contains(o.supportsPutFull))
+        require (m.supportsPutPartial.contains(o.supportsPutPartial))
+        require (m.supportsHint.contains(o.supportsHint))
+        require (m.fifoId == o.fifoId) // could relax this, but hard to validate
+      }
+      out
+    })})
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in  = node.bundleIn
+      val out = node.bundleOut
+    }
+    io.out <> io.in
+  }
+}
+
+object TLFilter
+{
+  def Midentity: TLManagerParameters => Option[TLManagerParameters] = { m => Some(m) }
+  def Cidentity: TLClientParameters => Option[TLClientParameters] = { c => Some(c) }
+  def Mmask(select: AddressSet): TLManagerParameters => Option[TLManagerParameters] = { m =>
     val filtered = m.address.map(_.intersect(select)).flatten
     val alignment = select.alignment /* alignment 0 means 'select' selected everything */
     val maxTransfer = 1 << 30
@@ -31,23 +79,23 @@ class TLFilter(select: AddressSet)(implicit p: Parameters) extends LazyModule
         supportsPutPartial = m.supportsPutPartial.intersect(cap),
         supportsHint       = m.supportsHint      .intersect(cap)))
     }
-      }.flatten)
-    })
-
-  lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
-      val in  = node.bundleIn
-      val out = node.bundleOut
   }
-    io.out <> io.in
+  def Mnocache: TLManagerParameters => Option[TLManagerParameters] = { m =>
+    if (m.supportsAcquireB) None else Some(m)
+  }
+  def Mcache: TLManagerParameters => Option[TLManagerParameters] = { m =>
+    if (m.supportsAcquireB) Some(m) else None
+  }
+  def Cnocache: TLClientParameters => Option[TLClientParameters] = { c =>
+    if (c.supportsProbe) None else Some(c)
   }
-}
 
-object TLFilter
-{
   // applied to the TL source node; y.node := TLBuffer(x.node)
-  def apply(select: AddressSet)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+  def apply(
-    val filter = LazyModule(new TLFilter(select))
+    Mfilter: TLManagerParameters => Option[TLManagerParameters] = TLFilter.Midentity,
+    Cfilter: TLClientParameters  => Option[TLClientParameters]  = TLFilter.Cidentity
+    )(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    val filter = LazyModule(new TLFilter(Mfilter, Cfilter))
     filter.node := x
     filter.node
   }

src/main/scala/tilelink/Map.scala

@@ -0,0 +1,54 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.tilelink
+
+import Chisel._
+import chisel3.internal.sourceinfo.SourceInfo
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import scala.math.{min,max}
+
+// Moves the AddressSets of slave devices around
+// Combine with TLFilter to remove slaves or reduce their size
+class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
+{
+  val node = TLAdapterNode(
+    clientFn = { cp => cp },
+    managerFn = { mp =>
+      mp.copy(managers = mp.managers.map(m =>
+        m.copy(address = m.address.map(a =>
+          AddressSet(fn(a), a.mask)))))})
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in = node.bundleIn
+      val out = node.bundleOut
+    }
+
+    io.out <> io.in
+
+    ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
+      val convert = edgeIn.manager.managers.flatMap(_.address) zip edgeOut.manager.managers.flatMap(_.address)
+      def forward(x: UInt) =
+        convert.map { case (i, o) => Mux(i.contains(x), UInt(o.base) | (x & UInt(o.mask)), UInt(0)) }.reduce(_ | _)
+      def backward(x: UInt) =
+        convert.map { case (i, o) => Mux(o.contains(x), UInt(i.base) | (x & UInt(i.mask)), UInt(0)) }.reduce(_ | _)
+
+      out.a.bits.address := forward(in.a.bits.address)
+      if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
+        out.c.bits.address := forward(in.c.bits.address)
+        in.b.bits.address := backward(out.b.bits.address)
+      }
+    }
+  }
+}
+
+object TLMap
+{
+  // applied to the TL source node; y.node := TLMap(fn)(x.node)
+  def apply(fn: AddressSet => BigInt)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    val map = LazyModule(new TLMap(fn))
+    map.node := x
+    map.node
+  }
+}