From 1577deb3242ceb708d9c74785a6fc8678c06bbcd Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 16:51:52 -0800 Subject: [PATCH 1/7] travis: delete oldest caches; not newest --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 2589aabb..e0a5b039 100644 --- a/.travis.yml +++ b/.travis.yml @@ -52,4 +52,4 @@ script: - make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default before_cache: - - ls -tr regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf + - ls -t regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf From ea3ec896760b2f2bfe99aeb0b8973e04c9d1dd10 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 15:12:05 -0800 Subject: [PATCH 2/7] travis: split RocketSuite into three smaller tests suites --- .travis.yml | 4 +++- regression/Makefile | 16 +++++++++++++--- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/.travis.yml b/.travis.yml index e0a5b039..28e03a88 100644 --- a/.travis.yml +++ b/.travis.yml @@ -33,7 +33,9 @@ addons: env: matrix: - - SUITE=RocketSuite + - SUITE=RocketSuiteA + - SUITE=RocketSuiteB + - SUITE=RocketSuiteC - SUITE=GroundtestSuite - SUITE=UnittestSuite diff --git a/regression/Makefile b/regression/Makefile index c520ebf9..ec0619f8 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -38,16 +38,26 @@ ifeq ($(SUITE),) $(error Set SUITE to the regression suite you want to run) endif -ifeq ($(SUITE),RocketSuite) +ifeq ($(SUITE),RocketSuiteA) PROJECT=rocketchip -CONFIGS=DefaultConfig DefaultBufferlessConfig TinyConfig +CONFIGS=DefaultConfig +endif + +ifeq ($(SUITE),RocketSuiteB) +PROJECT=rocketchip +CONFIGS=DefaultBufferlessConfig +endif + +ifeq ($(SUITE),RocketSuiteC) +PROJECT=rocketchip +CONFIGS=DefaultL2Config TinyConfig endif ifeq ($(SUITE),GroundtestSuite) PROJECT=groundtest CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \ BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \ - ComparatorConfig ComparatorBufferlessConfig ComparatorStatelessConfig + ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig endif ifeq ($(SUITE),UnittestSuite) From 3d1a7bd6d3d9d07eb84e9790546ddcfc038e5f0a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 17:37:14 -0800 Subject: [PATCH 3/7] travis: build verilator and toolchain as part of install --- .travis.yml | 3 +++ emulator/Makefrag-verilator | 2 ++ regression/Makefile | 2 ++ 3 files changed, 7 insertions(+) diff --git a/.travis.yml b/.travis.yml index 28e03a88..0ab1c95d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -46,6 +46,9 @@ branches: - boom - /^hurricane.*$/ +install: + - make tools verilator -C regression SUITE=none + before_install: - export CXX=g++-4.8 CC=gcc-4.8 diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator index 3f1fc17a..ea7c7e7d 100644 --- a/emulator/Makefrag-verilator +++ b/emulator/Makefrag-verilator @@ -46,6 +46,8 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ +verilator: $(INSTALLED_VERILATOR) + # Run Verilator to produce a fast binary to emulate this circuit. VERILATOR := $(INSTALLED_VERILATOR) --cc --exe VERILATOR_FLAGS := --top-module $(MODEL) \ diff --git a/regression/Makefile b/regression/Makefile index ec0619f8..a6322da2 100644 --- a/regression/Makefile +++ b/regression/Makefile @@ -78,6 +78,8 @@ endif # commandline a bit cleaner. submodules: stamps/other-submodules.stamp tools: $(RISCV)/install.stamp +verilator: + $(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/emulator) verilator EMU_DEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-debug.stamp) EMU_NDEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/emulator-ndebug.stamp) From c18bc07bbcd24b98a323669a1b65b52b7bf1dad3 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 11:48:10 -0800 Subject: [PATCH 4/7] TLB: determine RWX from TL2 properties directly --- src/main/scala/rocket/Dcache.scala | 2 +- src/main/scala/rocket/HellaCache.scala | 1 - src/main/scala/rocket/csr.scala | 1 - src/main/scala/rocket/rocket.scala | 7 +++-- src/main/scala/rocket/tile.scala | 17 ++++++----- src/main/scala/rocket/tlb.scala | 42 ++++++++++++++++---------- 6 files changed, 42 insertions(+), 28 deletions(-) diff --git a/src/main/scala/rocket/Dcache.scala b/src/main/scala/rocket/Dcache.scala index 4c44943f..5f91dee6 100644 --- a/src/main/scala/rocket/Dcache.scala +++ b/src/main/scala/rocket/Dcache.scala @@ -123,7 +123,7 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu require(nWays == 1) metaWriteArb.io.out.ready := true metaReadArb.io.out.ready := !metaWriteArb.io.out.valid - val inScratchpad = addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr) + val inScratchpad = Bool(false) // !!! addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr) val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) (inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset)) } else { diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index eb1a91f9..f8d3145b 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -145,7 +145,6 @@ class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends La with HasL1HellaCacheParameters { implicit val cfg = outer.cfg val io = new HellaCacheBundle(outer) - val edge = outer.node.edgesOut(0) val tl_out = io.mem(0) /* TODO diff --git a/src/main/scala/rocket/csr.scala b/src/main/scala/rocket/csr.scala index 4c67d2c2..82f59310 100644 --- a/src/main/scala/rocket/csr.scala +++ b/src/main/scala/rocket/csr.scala @@ -8,7 +8,6 @@ import config._ import uncore.devices._ import util._ import Chisel.ImplicitConversions._ -import junctions.AddrMap class MStatus extends Bundle { // not truly part of mstatus, but convenient diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala index ea350c84..7413d9b5 100644 --- a/src/main/scala/rocket/rocket.scala +++ b/src/main/scala/rocket/rocket.scala @@ -6,7 +6,7 @@ import Chisel._ import uncore.devices._ import uncore.agents.CacheName import uncore.constants._ -import junctions.HasAddrMapParameters +import uncore.tilelink2._ import util._ import Chisel.ImplicitConversions._ import config._ @@ -32,12 +32,14 @@ case object NBreakpoints extends Field[Int] case object NPerfCounters extends Field[Int] case object NPerfEvents extends Field[Int] case object DataScratchpadSize extends Field[Int] +case object TLCacheEdge extends Field[TLEdgeOut] -trait HasCoreParameters extends HasAddrMapParameters { +trait HasCoreParameters { implicit val p: Parameters val xLen = p(XLen) val fLen = xLen // TODO relax this + val edge = p(TLCacheEdge) val usingVM = p(UseVM) val usingUser = p(UseUser) || usingVM val usingDebug = p(UseDebug) @@ -67,6 +69,7 @@ trait HasCoreParameters extends HasAddrMapParameters { def pgIdxBits = 12 def pgLevelBits = 10 - log2Ceil(xLen / 32) def vaddrBits = pgIdxBits + pgLevels * pgLevelBits + val paddrBits = edge.bundle.addressBits def ppnBits = paddrBits - pgIdxBits def vpnBits = vaddrBits - pgIdxBits val pgLevels = p(PgLevels) diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala index 1ebc8836..6d0f4109 100644 --- a/src/main/scala/rocket/tile.scala +++ b/src/main/scala/rocket/tile.scala @@ -24,12 +24,15 @@ case class RoccParameters( useFPU: Boolean = false) class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { - val dcacheParams = p.alterPartial({ + val coreParams = p.alterPartial { + case TLCacheEdge => cachedOut.edgesOut(0) + } + val dcacheParams = coreParams.alterPartial({ case CacheName => CacheName("L1D") case TLId => "L1toL2" case TileId => tileId // TODO using this messes with Heirarchical P&R: change to io.hartid? }) - val icacheParams = p.alterPartial({ + val icacheParams = coreParams.alterPartial({ case CacheName => CacheName("L1I") case TLId => "L1toL2" }) @@ -54,7 +57,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { val uncached = uncachedOut.bundleOut val slave = slaveNode.map(_.bundleIn) val hartid = UInt(INPUT, p(XLen)) - val interrupts = new TileInterrupts().asInput + val interrupts = new TileInterrupts()(coreParams).asInput val resetVector = UInt(INPUT, p(XLen)) } @@ -74,15 +77,15 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { icache.io.cpu <> core.io.imem icache.io.resetVector := io.resetVector - val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg))) + val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)(coreParams))) fpuOpt.foreach(fpu => core.io.fpu <> fpu.io) if (usingRocc) { - val respArb = Module(new RRArbiter(new RoCCResponse, nRocc)) + val respArb = Module(new RRArbiter(new RoCCResponse()(coreParams), nRocc)) core.io.rocc.resp <> respArb.io.out val roccOpcodes = buildRocc.map(_.opcodes) - val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)) + val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)(coreParams)) cmdRouter.io.in <> core.io.rocc.cmd val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) => @@ -101,7 +104,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { if (nFPUPorts > 0) { fpuOpt.foreach { fpu => - val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts)) + val fpArb = Module(new InOrderArbiter(new FPInput()(coreParams), new FPResult()(coreParams), nFPUPorts)) val fp_roccs = roccs.zip(buildRocc) .filter { case (_, params) => params.useFPU } .map { case (rocc, _) => rocc.io } diff --git a/src/main/scala/rocket/tlb.scala b/src/main/scala/rocket/tlb.scala index 339f2e84..86020004 100644 --- a/src/main/scala/rocket/tlb.scala +++ b/src/main/scala/rocket/tlb.scala @@ -5,17 +5,19 @@ package rocket import Chisel._ import util._ import Chisel.ImplicitConversions._ -import junctions._ import scala.math._ import config._ +import diplomacy._ import uncore.agents._ import uncore.coherence._ +import uncore.tilelink2._ case object PgLevels extends Field[Int] case object ASIdBits extends Field[Int] trait HasTLBParameters extends HasCoreParameters { val entries = p(p(CacheName)).nTLBEntries + val cacheBlockBytes = p(CacheBlockBytes) val camAddrBits = log2Ceil(entries) val camTagBits = asIdBits + vpnBits } @@ -64,15 +66,23 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters { val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) val do_refill = Bool(usingVM) && io.ptw.resp.valid val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn) - val prot = addrMap.getProt(mpu_ppn << pgIdxBits) - val cacheable = addrMap.isCacheable(mpu_ppn << pgIdxBits) - def pgaligned(r: MemRegion) = { - val pgsize = 1 << pgIdxBits - (r.start % pgsize) == 0 && (r.size % pgsize) == 0 + def fastCheck(member: TLManagerParameters => Boolean) = + Mux1H(edge.manager.findFast(mpu_ppn << pgIdxBits), edge.manager.managers.map(m => Bool(member(m)))) + val prot_r = fastCheck(_.supportsGet) + val prot_w = fastCheck(_.supportsPutFull) + val prot_x = fastCheck(_.executable) + val cacheable = fastCheck(_.supportsAcquire) + val allSizes = TransferSizes(1, cacheBlockBytes) + val amoSizes = TransferSizes(1, xLen/8) + edge.manager.managers.foreach { m => + require (m.minAlignment >= 4096, s"MemoryMap region ${m.name} must be page-aligned (is ${m.minAlignment})") + require (!m.supportsGet || m.supportsGet .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsGet} Get, but must support ${allSizes}") + require (!m.supportsPutFull || m.supportsPutFull.contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") + require (!m.supportsAcquire || m.supportsAcquire.contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquire} Acquire, but must support ${allSizes}") + require (!m.supportsLogical || m.supportsLogical.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") + require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") } - require(addrMap.flatten.forall(e => pgaligned(e.region)), - "MemoryMap regions must be page-aligned") - + val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0)) val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough val hitsVec = (0 until entries).map(i => valid(i) && vm_enabled && tags(i) === lookup_tag) :+ !vm_enabled @@ -95,10 +105,10 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters { val mask = UIntToOH(r_refill_waddr) valid := valid | mask u_array := Mux(pte.u, u_array | mask, u_array & ~mask) - sw_array := Mux(pte.sw() && prot.w, sw_array | mask, sw_array & ~mask) - sx_array := Mux(pte.sx() && prot.x, sx_array | mask, sx_array & ~mask) - sr_array := Mux(pte.sr() && prot.r, sr_array | mask, sr_array & ~mask) - xr_array := Mux(pte.sx() && prot.r, xr_array | mask, xr_array & ~mask) + sw_array := Mux(pte.sw() && prot_w, sw_array | mask, sw_array & ~mask) + sx_array := Mux(pte.sx() && prot_x, sx_array | mask, sx_array & ~mask) + sr_array := Mux(pte.sr() && prot_r, sr_array | mask, sr_array & ~mask) + xr_array := Mux(pte.sx() && prot_r, xr_array | mask, xr_array & ~mask) cash_array := Mux(cacheable, cash_array | mask, cash_array & ~mask) dirty_array := Mux(pte.d, dirty_array | mask, dirty_array & ~mask) } @@ -107,9 +117,9 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters { val repl_waddr = Mux(!valid.andR, PriorityEncoder(~valid), plru.replace) val priv_ok = Mux(priv_s, ~Mux(io.ptw.status.pum, u_array, UInt(0)), u_array) - val w_array = Cat(prot.w, priv_ok & sw_array) - val x_array = Cat(prot.x, priv_ok & sx_array) - val r_array = Cat(prot.r, priv_ok & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0)))) + val w_array = Cat(prot_w, priv_ok & sw_array) + val x_array = Cat(prot_x, priv_ok & sx_array) + val r_array = Cat(prot_r, priv_ok & (sr_array | Mux(io.ptw.status.mxr, xr_array, UInt(0)))) val c_array = Cat(cacheable, cash_array) val bad_va = From 5fe107bb071160bb21a17a4e41e2d1210b49d35f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 12:19:33 -0800 Subject: [PATCH 5/7] rocket: pass scratchpad address to block dcache --- src/main/scala/groundtest/Tile.scala | 7 +++++-- src/main/scala/rocket/Dcache.scala | 4 ++-- src/main/scala/rocket/HellaCache.scala | 4 ++-- src/main/scala/rocket/NBDcache.scala | 1 + src/main/scala/rocket/ScratchpadSlavePort.scala | 8 ++------ src/main/scala/rocket/tile.scala | 9 ++++++++- 6 files changed, 20 insertions(+), 13 deletions(-) diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index d889bfb3..5f002844 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -100,7 +100,10 @@ abstract class GroundTest(implicit val p: Parameters) extends Module } class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGroundTestParameters { - val dcacheParams = p.alterPartial({ case CacheName => CacheName("L1D") }) + val dcacheParams = p.alterPartial { + case CacheName => CacheName("L1D") + case rocket.TLCacheEdge => cachedOut.edgesOut(0) + } val slave = None val dcache = HellaCache(p(DCacheKey))(dcacheParams) val ucLegacy = LazyModule(new TLLegacy()(p)) @@ -141,7 +144,7 @@ class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGrou } if (ptwPorts.size > 0) { - val ptw = Module(new DummyPTW(ptwPorts.size)) + val ptw = Module(new DummyPTW(ptwPorts.size)(dcacheParams)) ptw.io.requestors <> ptwPorts } diff --git a/src/main/scala/rocket/Dcache.scala b/src/main/scala/rocket/Dcache.scala index 5f91dee6..5027e8c4 100644 --- a/src/main/scala/rocket/Dcache.scala +++ b/src/main/scala/rocket/Dcache.scala @@ -39,7 +39,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { } } -class DCache(cfg: DCacheConfig)(implicit p: Parameters) extends HellaCache(cfg)(p) { +class DCache(cfg: DCacheConfig, val scratch: () => Option[AddressSet])(implicit p: Parameters) extends HellaCache(cfg)(p) { override lazy val module = new DCacheModule(this) } @@ -123,7 +123,7 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu require(nWays == 1) metaWriteArb.io.out.ready := true metaReadArb.io.out.ready := !metaWriteArb.io.out.valid - val inScratchpad = Bool(false) // !!! addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr) + val inScratchpad = outer.scratch().map(_.contains(s1_paddr)).getOrElse(Bool(false)) val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) (inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset)) } else { diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index f8d3145b..6a783e80 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -159,8 +159,8 @@ class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends La } object HellaCache { - def apply(cfg: DCacheConfig)(implicit p: Parameters) = { - if (cfg.nMSHRs == 0) LazyModule(new DCache(cfg)) + def apply(cfg: DCacheConfig, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = { + if (cfg.nMSHRs == 0) LazyModule(new DCache(cfg, scratch)) else LazyModule(new NonBlockingDCache(cfg)) } } diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index 8858d51f..5c4ecc10 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -687,6 +687,7 @@ class NonBlockingDCache(cfg: DCacheConfig)(implicit p: Parameters) extends Hella class NonBlockingDCacheModule(outer: NonBlockingDCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) { require(isPow2(nWays)) // TODO: relax this + require(p(DataScratchpadSize) == 0) val wb = Module(new WritebackUnit(edge)) val prober = Module(new ProbeUnit(edge)) diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index b766082a..ab7d25c6 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -11,7 +11,8 @@ import uncore.constants._ import uncore.tilelink2._ import uncore.util._ -class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with HasCoreParameters { +class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule { + val coreDataBytes = p(XLen)/8 val node = TLManagerNode(TLManagerPortParameters( Seq(TLManagerParameters( address = List(AddressSet(0x80000000L, BigInt(p(DataScratchpadSize)-1))), @@ -26,9 +27,6 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha beatBytes = coreDataBytes, minLatency = 1)) - // Make sure this ends up with the same name as before - override def name = "dmem0" - lazy val module = new LazyModuleImp(this) { val io = new Bundle { val tl_in = node.bundleIn @@ -38,8 +36,6 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha val tl_in = io.tl_in(0) val edge = node.edgesIn(0) - require(usingDataScratchpad) - val s_ready :: s_wait :: s_replay :: s_grant :: Nil = Enum(UInt(), 4) val state = Reg(init = s_ready) when (io.dmem.resp.valid) { state := s_grant } diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala index 6d0f4109..e0b7a585 100644 --- a/src/main/scala/rocket/tile.scala +++ b/src/main/scala/rocket/tile.scala @@ -40,7 +40,14 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { //TODO val intNode = IntInputNode() val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode()) val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams))) - val dcache = HellaCache(p(DCacheKey))(dcacheParams) + def findScratch() = scratch.map { s => + val finalNode = uncachedOut.edgesOut(0).manager.managers.find(_.nodePath.last == s.node) + require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?") + require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!") + finalNode.get.address(0) + } + + val dcache = HellaCache(p(DCacheKey), findScratch)(dcacheParams) val ucLegacy = LazyModule(new TLLegacy()(icacheParams)) val cachedOut = TLOutputNode() From e8be365b5d5e61f340966c9ff0dcf2ea2d1252e1 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 12:45:00 -0800 Subject: [PATCH 6/7] rocketchip: remove GlobalAddrMap completely --- src/main/scala/coreplex/BaseCoreplex.scala | 13 +++++++++ src/main/scala/coreplex/RISCVPlatform.scala | 27 ++++++------------- src/main/scala/junctions/addrmap.scala | 7 ----- src/main/scala/rocketchip/BaseTop.scala | 9 +------ src/main/scala/rocketchip/Utils.scala | 30 --------------------- 5 files changed, 22 insertions(+), 64 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 21255209..dd9b9c6e 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -104,6 +104,19 @@ trait CoreplexNetworkModule extends HasCoreplexParameters { val io: CoreplexNetworkBundle implicit val p = outer.p + + { + println("\nGenerated Address Map") + for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) { + val prot = (if (manager.supportsGet) "R" else "") + + (if (manager.supportsPutFull) "W" else "") + + (if (manager.executable) "X" else "") + + (if (manager.supportsAcquire) " [C]" else "") + manager.address.foreach { a => + println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot") + } + } + } } trait BankedL2CoherenceManagers extends CoreplexNetwork { diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala index 18fb9368..e379aaeb 100644 --- a/src/main/scala/coreplex/RISCVPlatform.scala +++ b/src/main/scala/coreplex/RISCVPlatform.scala @@ -48,25 +48,14 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule { val rtcLast = Reg(init = Bool(false), next=rtcSync) outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast))) - println("\nGenerated Address Map") - for (entry <- p(rocketchip.GlobalAddrMap).flatten) { - val name = entry.name - val start = entry.region.start - val end = entry.region.start + entry.region.size - 1 - val prot = entry.region.attr.prot - val protStr = (if ((prot & AddrMapProt.R) > 0) "R" else "") + - (if ((prot & AddrMapProt.W) > 0) "W" else "") + - (if ((prot & AddrMapProt.X) > 0) "X" else "") - val cacheable = if (entry.region.attr.cacheable) " [C]" else "" - println(f"\t$name%s $start%x - $end%x, $protStr$cacheable") - } + { + val managers = outer.l1tol2.node.edgesIn(0).manager.managers - // Create and export the ConfigString - val managers = outer.l1tol2.node.edgesIn(0).manager.managers - val configString = rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers) - // Allow something else to have override the config string - if (!ConfigStringOutput.contents.isDefined) { - ConfigStringOutput.contents = Some(configString) + // Allow something else to have override the config string + if (!ConfigStringOutput.contents.isDefined) { + ConfigStringOutput.contents = Some(rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers)) + } + + println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}") } - println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}") } diff --git a/src/main/scala/junctions/addrmap.scala b/src/main/scala/junctions/addrmap.scala index a94ea32d..787f9ab1 100644 --- a/src/main/scala/junctions/addrmap.scala +++ b/src/main/scala/junctions/addrmap.scala @@ -8,13 +8,6 @@ import scala.collection.mutable.HashMap case object PAddrBits extends Field[Int] -trait HasAddrMapParameters { - implicit val p: Parameters - - val paddrBits = p(PAddrBits) - def addrMap = p(rocketchip.GlobalAddrMap) -} - case class MemAttr(prot: Int, cacheable: Boolean = false) sealed abstract class MemRegion { diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index a5f100ab..76055561 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -13,18 +13,11 @@ import util._ import rocket._ import coreplex._ -// the following parameters will be refactored properly with TL2 -case object GlobalAddrMap extends Field[AddrMap] /** Enable or disable monitoring of Diplomatic buses */ case object TLEmitMonitors extends Field[Boolean] abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule { - // Fill in the TL1 legacy parameters; remove these once rocket/groundtest/unittest are TL2 - lazy val legacyAddrMap = GenerateGlobalAddrMap(p, coreplex.l1tol2.node.edgesIn(0).manager.managers) - val coreplex : C = LazyModule(_coreplex(p.alterPartial { - case GlobalAddrMap => legacyAddrMap - })) - + val coreplex = LazyModule(_coreplex(p)) TopModule.contents = Some(this) } diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala index f0aaeb9d..f8b3e3f4 100644 --- a/src/main/scala/rocketchip/Utils.scala +++ b/src/main/scala/rocketchip/Utils.scala @@ -52,36 +52,6 @@ class GlobalVariable[T] { def get: T = { require(assigned); variable } } -object GenerateGlobalAddrMap { - def apply(p: Parameters, peripheryManagers: Seq[TLManagerParameters]) = { - val tl2Devices = peripheryManagers.map { manager => - val cacheable = manager.regionType match { - case RegionType.CACHED => true - case RegionType.TRACKED => true - case _ => false - } - val attr = MemAttr( - (if (manager.supportsGet) AddrMapProt.R else 0) | - (if (manager.supportsPutFull) AddrMapProt.W else 0) | - (if (manager.executable) AddrMapProt.X else 0), cacheable) - val multi = manager.address.size > 1 - manager.address.zipWithIndex.map { case (address, i) => - require (address.contiguous) // TL1 needs this - val name = manager.name + (if (multi) ".%d".format(i) else "") - AddrMapEntry(name, MemRange(address.base, address.mask+1, attr)) - } - }.flatten - - val uniquelyNamedTL2Devices = - tl2Devices.groupBy(_.name).values.map(_.zipWithIndex.map { - case (e, i) => if (i == 0) e else e.copy(name = e.name + "_" + i) - }).flatten.toList - - val tl2 = AddrMapEntry("TL2", new AddrMap(uniquelyNamedTL2Devices, collapse = true)) - AddrMap(tl2) - } -} - object GenerateConfigString { def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = { val c = CoreplexParameters()(p) From 3d644b943cf59408d4f5fd9b526e9ede4139c1f7 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 21 Nov 2016 16:11:16 -0800 Subject: [PATCH 7/7] coreplex: configString is a property of the RISCVPlatform --- src/main/scala/coreplex/BaseCoreplex.scala | 18 ++++++++---------- src/main/scala/coreplex/RISCVPlatform.scala | 17 +++++++---------- src/main/scala/rocketchip/ExampleTop.scala | 6 +++--- src/main/scala/rocketchip/Periphery.scala | 8 +++++--- src/main/scala/rocketchip/Utils.scala | 4 ++-- 5 files changed, 25 insertions(+), 28 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index dd9b9c6e..75325802 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -105,16 +105,14 @@ trait CoreplexNetworkModule extends HasCoreplexParameters { implicit val p = outer.p - { - println("\nGenerated Address Map") - for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) { - val prot = (if (manager.supportsGet) "R" else "") + - (if (manager.supportsPutFull) "W" else "") + - (if (manager.executable) "X" else "") + - (if (manager.supportsAcquire) " [C]" else "") - manager.address.foreach { a => - println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot") - } + println("\nGenerated Address Map") + for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) { + val prot = (if (manager.supportsGet) "R" else "") + + (if (manager.supportsPutFull) "W" else "") + + (if (manager.executable) "X" else "") + + (if (manager.supportsAcquire) " [C]" else "") + manager.address.foreach { a => + println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot") } } } diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala index e379aaeb..804854d4 100644 --- a/src/main/scala/coreplex/RISCVPlatform.scala +++ b/src/main/scala/coreplex/RISCVPlatform.scala @@ -26,6 +26,11 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork { clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) plic.intnode := intBar.intnode + + lazy val configString = { + val managers = l1tol2.node.edgesIn(0).manager.managers + rocketchip.GenerateConfigString(p, clint, plic, managers) + } } trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle { @@ -48,14 +53,6 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule { val rtcLast = Reg(init = Bool(false), next=rtcSync) outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast))) - { - val managers = outer.l1tol2.node.edgesIn(0).manager.managers - - // Allow something else to have override the config string - if (!ConfigStringOutput.contents.isDefined) { - ConfigStringOutput.contents = Some(rocketchip.GenerateConfigString(p, outer.clint, outer.plic, managers)) - } - - println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}") - } + println(s"\nGenerated Configuration String\n${outer.configString}") + ConfigStringOutput.contents = Some(outer.configString) } diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala index a8ff4adf..00cafe31 100644 --- a/src/main/scala/rocketchip/ExampleTop.scala +++ b/src/main/scala/rocketchip/ExampleTop.scala @@ -11,7 +11,6 @@ import rocketchip._ /** Example Top with Periphery */ class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex) with DirectConnection - with PeripheryBootROM with PeripheryExtInterrupts with PeripheryMasterAXI4Mem with PeripheryMasterAXI4MMIO { @@ -19,18 +18,17 @@ class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Par } class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer) - with PeripheryBootROMBundle with PeripheryExtInterruptsBundle with PeripheryMasterAXI4MemBundle with PeripheryMasterAXI4MMIOBundle class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) - with PeripheryBootROMModule with PeripheryExtInterruptsModule with PeripheryMasterAXI4MemModule with PeripheryMasterAXI4MMIOModule class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex) + with PeripheryBootROM with PeripheryDTM with PeripheryCounter with HardwiredResetVector { @@ -38,11 +36,13 @@ class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implic } class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer) + with PeripheryBootROMBundle with PeripheryDTMBundle with PeripheryCounterBundle with HardwiredResetVectorBundle class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) + with PeripheryBootROMModule with PeripheryDTMModule with PeripheryCounterModule with HardwiredResetVectorModule diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index aaf6fd4f..3cc38035 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -156,10 +156,12 @@ trait PeripheryMasterAXI4MMIOModule { trait PeripheryBootROM { this: TopNetwork => + val coreplex: CoreplexRISCVPlatform - val bootrom_address = 0x1000 - val bootrom_size = 0x1000 - val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, GenerateBootROM(p, bootrom_address), true, peripheryBusConfig.beatBytes)) + private val bootrom_address = 0x1000 + private val bootrom_size = 0x1000 + private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString) + val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes)) bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) } diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala index f8b3e3f4..bcf54049 100644 --- a/src/main/scala/rocketchip/Utils.scala +++ b/src/main/scala/rocketchip/Utils.scala @@ -84,7 +84,7 @@ object GenerateConfigString { } object GenerateBootROM { - def apply(p: Parameters, address: BigInt) = { + def apply(p: Parameters, address: BigInt, configString: String) = { val romdata = Files.readAllBytes(Paths.get(p(BootROMFile))) val rom = ByteBuffer.wrap(romdata) @@ -95,6 +95,6 @@ object GenerateBootROM { require(rom.getInt(12) == 0, "Config string address position should not be occupied by code") rom.putInt(12, configStringAddr) - rom.array() ++ (ConfigStringOutput.contents.get.getBytes.toSeq) + rom.array() ++ (configString.getBytes.toSeq) } }