riscv/rocket-chip
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Allow some External Interrupts to come from Periphery

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This commit is contained in:
Megan Wachs
2016-08-25 10:04:31 -07:00
parent 8ff739d3fa
commit 428eed79a1
4 changed files with 34 additions and 13 deletions
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8
src/main/scala/rocketchip/TestConfigs.scala
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@ -189,12 +189,14 @@ class WithBusMasterTest extends Config(
def addrMapEntries = Seq(
AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW))))
def builder(
mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
clientPorts: Seq[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters) {
mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
clientPorts: Seq[ClientUncachedTileLinkIO],
interrupts : Seq[Bool],
extra: Bundle, p: Parameters) {
val busmaster = Module(new ExampleBusMaster()(p))
busmaster.io.mmio <> mmioPorts("busmaster")
clientPorts.head <> busmaster.io.mem
interrupts.foreach(x => x := Bool(false))
}
}
new BusMasterDevice