riscv/rocket-chip
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Allow some External Interrupts to come from Periphery

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This commit is contained in:
Megan Wachs
2016-08-25 10:04:31 -07:00
parent 8ff739d3fa
commit 428eed79a1
4 changed files with 34 additions and 13 deletions
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13
src/main/scala/rocketchip/Configs.scala
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@ -115,7 +115,10 @@ class BasePlatformConfig extends Config (
idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
}
case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
case NExtInterrupts => 2
case NExtTopInterrupts => 2
case NExtPeripheryInterrupts => 0
// Note that PLIC asserts that this is > 0.
case NExtInterrupts => site(NExtTopInterrupts) + site(NExtPeripheryInterrupts)
case AsyncDebugBus => false
case IncludeJtagDTM => false
case AsyncMMIOChannels => false
@ -260,11 +263,13 @@ class WithTestRAM extends Config(
def addrMapEntries = Seq(
AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))))
def builder(
mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
clientPorts: Seq[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters) {
mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
clientPorts: Seq[ClientUncachedTileLinkIO],
interrupts: Seq[Bool],
extra: Bundle, p: Parameters) {
val testram = Module(new TileLinkTestRAM(ramSize)(p))
testram.io <> mmioPorts("testram")
interrupts.foreach(x => x := Bool(false))
}
}
new TestRAMDevice