riscv/rocket-chip
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Emulator: Update it to allow some hard-coded Verilog PlusArgs

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This commit is contained in:
Megan Wachs 2018-01-03 16:55:48 -08:00
parent 76c5fd0c0c
commit 427b6c9ab8
1 changed files with 40 additions and 5 deletions
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43
csrc/emulator.cc
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@ -15,6 +15,13 @@
#include <unistd.h> #include <unistd.h>
#include <getopt.h> #include <getopt.h>
//TODO: GENERATE THESE AUTOMATICALLY!
static const char * verilog_plusargs [] = { "max-core-cycles",
"jtag_rbb_enable",
"tilelink_timeout",
0};
extern dtm_t* dtm; extern dtm_t* dtm;
extern remote_bitbang_t * jtag; extern remote_bitbang_t * jtag;
@ -39,7 +46,7 @@ extern "C" int vpi_get_vlog_info(void* arg)
static void usage(const char * program_name) static void usage(const char * program_name)
{ {
printf("Usage: %s [EMULATOR OPTION]... [HOST OPTION]... BINARY [TARGET OPTION]...\n", printf("Usage: %s [EMULATOR OPTION]... [VERILOG PLUSARG]... [HOST OPTION]... BINARY [TARGET OPTION]...\n",
program_name); program_name);
fputs("\ fputs("\
Run a BINARY on the Rocket Chip emulator.\n\ Run a BINARY on the Rocket Chip emulator.\n\
@ -67,6 +74,14 @@ EMULATOR OPTIONS (only supported in debug build -- try `make debug`)\n",
-x, --dump-start=CYCLE Start VCD tracing at CYCLE\n\ -x, --dump-start=CYCLE Start VCD tracing at CYCLE\n\
+dump-start\n\ +dump-start\n\
", stdout); ", stdout);
fputs("\
\n\
VERILOG PLUSARGS (accepted by the Verilog itself):\n" , stdout);
const char ** vpa = &verilog_plusargs[0];
while (*vpa) {
fprintf(stdout, " +%s=...\n", *vpa);
vpa ++;
}
fputs("\n" HTIF_USAGE_OPTIONS, stdout); fputs("\n" HTIF_USAGE_OPTIONS, stdout);
printf("\n" printf("\n"
"EXAMPLES\n" "EXAMPLES\n"
@ -94,6 +109,7 @@ int main(int argc, char** argv)
uint64_t start = 0; uint64_t start = 0;
#endif #endif
char ** htif_argv = NULL; char ** htif_argv = NULL;
int verilog_plusargs_legal = 1;
while (1) { while (1) {
static struct option long_options[] = { static struct option long_options[] = {
@ -157,9 +173,27 @@ int main(int argc, char** argv)
#endif #endif
else if (arg.substr(0, 12) == "+cycle-count") else if (arg.substr(0, 12) == "+cycle-count")
c = 'c'; c = 'c';
// If we don't find a legacy '+' argument, it still could be // If we don't find a legacy '+' EMULATOR argument, it still could be
// an HTIF (HOST) argument and not an error. If this is the // a VERILOG_PLUSARG and not an error.
// case, then we're done processing EMULATOR arguments. else if (verilog_plusargs_legal) {
const char ** plusarg = &verilog_plusargs[0];
int legal_verilog_plusarg = 0;
while (*plusarg && (legal_verilog_plusarg == 0)){
if (arg.substr(1, strlen(*plusarg)) == *plusarg) {
legal_verilog_plusarg = 1;
}
plusarg ++;
}
if (!legal_verilog_plusarg) {
verilog_plusargs_legal = 0;
} else {
c = 'P';
}
goto retry;
}
// If we STILL don't find a legacy '+' argument, it still could be
// an HTIF (HOST) argument and not an error. If this is the case, then
// we're done processing EMULATOR and VERILOG arguments.
else { else {
static struct option htif_long_options [] = { HTIF_LONG_OPTIONS }; static struct option htif_long_options [] = { HTIF_LONG_OPTIONS };
struct option * htif_option = &htif_long_options[0]; struct option * htif_option = &htif_long_options[0];
@ -175,6 +209,7 @@ int main(int argc, char** argv)
} }
goto retry; goto retry;
} }
case 'P': break; // Nothing to do here, Verilog PlusArg
// Realize that we've hit HTIF (HOST) arguments or error out // Realize that we've hit HTIF (HOST) arguments or error out
default: default:
if (c >= HTIF_LONG_OPTIONS_OPTIND) { if (c >= HTIF_LONG_OPTIONS_OPTIND) {