riscv/rocket-chip
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Write instruction to badaddr on illegal instruction traps

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This commit is contained in:
Andrew Waterman 2017-03-27 22:06:52 -07:00 committed by Andrew Waterman
parent ed38787c36
commit 4215f480ef
2 changed files with 17 additions and 7 deletions
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5
src/main/scala/rocket/CSR.scala
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@ -498,11 +498,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
when (exception) { when (exception) {
val epc = ~(~io.pc | (coreInstBytes-1)) val epc = ~(~io.pc | (coreInstBytes-1))
val write_badaddr = cause isOneOf (Causes.breakpoint, val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch, Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
Causes.load_access, Causes.store_access, Causes.fetch_access, Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
)
when (trapToDebug) { when (trapToDebug) {
reg_debug := true reg_debug := true

19
src/main/scala/rocket/Rocket.scala
View File

@ -297,9 +297,14 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
ex_ctrl.alu_fn := ALU.FN_ADD ex_ctrl.alu_fn := ALU.FN_ADD
ex_ctrl.alu_dw := DW_XPR ex_ctrl.alu_dw := DW_XPR
ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction
ex_ctrl.sel_alu2 := A2_ZERO ex_ctrl.sel_alu2 := A2_ZERO
when (!bpu.io.xcpt_if && !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1) { // PC+2 when (bpu.io.xcpt_if || id_xcpt_pf || id_xcpt_ae) { // badaddr := PC
ex_ctrl.sel_alu1 := A1_PC
}
val pf_second = !ibuf.io.inst(0).bits.pf0 && ibuf.io.inst(0).bits.pf1
val ae_second = !ibuf.io.inst(0).bits.ae0 && ibuf.io.inst(0).bits.ae1
when (!bpu.io.xcpt_if && (pf_second || (!id_xcpt_pf && ae_second))) { // badaddr := PC+2
ex_ctrl.sel_alu2 := A2_SIZE ex_ctrl.sel_alu2 := A2_SIZE
ex_reg_rvc := true ex_reg_rvc := true
} }
@ -316,10 +321,16 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_bypass(i) := do_bypass
ex_reg_rs_lsb(i) := bypass_src ex_reg_rs_lsb(i) := bypass_src
when (id_ren(i) && !do_bypass) { when (id_ren(i) && !do_bypass) {
ex_reg_rs_lsb(i) := id_rs(i)(bypass_src.getWidth-1,0) ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(i) := id_rs(i) >> bypass_src.getWidth ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size)
} }
} }
when (id_illegal_insn) {
val inst = Mux(ibuf.io.inst(0).bits.rvc, ibuf.io.inst(0).bits.raw(15, 0), ibuf.io.inst(0).bits.raw)
ex_reg_rs_bypass(0) := false
ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size)
}
} }
when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) { when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
ex_reg_cause := id_cause ex_reg_cause := id_cause