riscv/rocket-chip
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Write instruction to badaddr on illegal instruction traps

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This commit is contained in:
Andrew Waterman
2017-03-27 22:06:52 -07:00
committed by Andrew Waterman
parent ed38787c36
commit 4215f480ef
2 changed files with 17 additions and 7 deletions
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5
src/main/scala/rocket/CSR.scala
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@ -498,11 +498,10 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
when (exception) {
val epc = ~(~io.pc | (coreInstBytes-1))
val write_badaddr = cause isOneOf (Causes.breakpoint,
val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault
)
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
when (trapToDebug) {
reg_debug := true