riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts

Browse Source
This commit is contained in:
Megan Wachs 2016-08-26 09:32:36 -07:00
commit 41aa80c5d7
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/rocket/nbdcache.scala
View File

@ -755,13 +755,13 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val rway_en = io.read.bits.way_en(w+rowWords-1,w) val rway_en = io.read.bits.way_en(w+rowWords-1,w)
val resp = Wire(Vec(rowWords, Bits(width = encRowBits))) val resp = Wire(Vec(rowWords, Bits(width = encRowBits)))
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid) val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (p <- 0 until resp.size) { for (i <- 0 until resp.size) {
val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits))) val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) { when (wway_en.orR && io.write.valid && io.write.bits.wmask(i)) {
val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p)) val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
array.write(waddr, data, wway_en.toBools) array.write(waddr, data, wway_en.toBools)
} }
resp(p) := array.read(raddr, rway_en.orR && io.read.valid).asUInt resp(i) := array.read(raddr, rway_en.orR && io.read.valid).asUInt
} }
for (dw <- 0 until rowWords) { for (dw <- 0 until rowWords) {
val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw))) val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))