Add Instruction Tightly Integrated Memory
This commit is contained in:
Andrew Waterman
parent
ee6702e5e0
commit
418879a47f
@ -42,10 +42,15 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val acquire = Bool(INPUT)
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}
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class Frontend(implicit p: Parameters) extends LazyModule {
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class Frontend(hartid: Int)(implicit p: Parameters) extends LazyModule {
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lazy val module = new FrontendModule(this)
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val icache = LazyModule(new ICache(latency = 2))
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val icache = LazyModule(new ICache(latency = 2, hartid))
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val node = TLOutputNode()
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val slaveNode = icache.slaveNode.map { n =>
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val res = TLInputNode()
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n := res
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res
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}
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node := icache.node
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}
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@ -53,8 +58,10 @@ class Frontend(implicit p: Parameters) extends LazyModule {
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class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
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val cpu = new FrontendIO().flip
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val ptw = new TLBPTWIO()
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val mem = outer.node.bundleOut
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val tl_out = outer.node.bundleOut
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val tl_in = outer.slaveNode.map(_.bundleIn)
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val resetVector = UInt(INPUT, vaddrBitsExtended)
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val hartid = UInt(INPUT, p(XLen))
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}
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class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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@ -68,8 +75,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 3, flow = true)) }
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val s0_valid = io.cpu.req.valid || fq.io.enq.ready
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val s1_pc_ = Reg(UInt(width=vaddrBitsExtended))
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val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
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val s1_pc = Reg(UInt(width=vaddrBitsExtended))
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val s1_speculative = Reg(Bool())
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val s2_valid = Reg(init=Bool(true))
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val s2_pc = Reg(init=io.resetVector)
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@ -94,7 +100,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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s2_replay := (s2_valid && !fq.io.enq.fire()) || RegNext(s2_replay && !s0_valid)
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val npc = Mux(s2_replay, s2_pc, predicted_npc)
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s1_pc_ := io.cpu.npc
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s1_pc := io.cpu.npc
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// consider RVC fetches across blocks to be non-speculative if the first
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// part was non-speculative
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val s0_speculative =
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@ -116,7 +122,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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if (usingBTB) {
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val btb = Module(new BTB)
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc_
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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@ -148,16 +154,18 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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tlb.io.req.bits.sfence := io.cpu.sfence
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tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)
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icache.io.hartid := io.hartid
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icache.io.req.valid := s0_valid
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icache.io.req.bits.addr := io.cpu.npc
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_paddr := tlb.io.resp.paddr
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icache.io.s2_vaddr := s2_pc
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icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || s2_replay
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icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt
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fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill)
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fq.io.enq.bits.pc := s2_pc
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io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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io.cpu.npc := ~(~Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) | (coreInstBytes-1)) // discard LSB(s)
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fq.io.enq.bits.data := icache.io.resp.bits
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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@ -170,13 +178,14 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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io.cpu.resp <> fq.io.deq
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// performance events
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io.cpu.acquire := edge.done(icache.io.mem(0).a)
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io.cpu.acquire := edge.done(icache.io.tl_out(0).a)
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}
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/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
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trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
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val module: HasICacheFrontendModule
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val frontend = LazyModule(new Frontend)
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val frontend = LazyModule(new Frontend(hartid: Int))
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val hartid: Int
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masterNode := frontend.node
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nPTWPorts += 1
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}
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@ -19,6 +19,7 @@ case class ICacheParams(
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nTLBEntries: Int = 32,
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cacheIdBits: Int = 0,
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ecc: Option[Code] = None,
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itimAddr: Option[BigInt] = None,
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blockBytes: Int = 64) extends L1CacheParams {
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def replacement = new RandomReplacement(nWays)
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}
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@ -31,65 +32,115 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
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val addr = UInt(width = vaddrBits)
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}
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class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
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val data = Bits(width = coreInstBits)
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val datablock = Bits(width = rowBits)
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}
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class ICache(val latency: Int)(implicit p: Parameters) extends LazyModule {
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class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends LazyModule
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with HasRocketCoreParameters {
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lazy val module = new ICacheModule(this)
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val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
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val icacheParams = tileParams.icache.get
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val slaveNode = icacheParams.itimAddr.map { itimAddr =>
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val wordBytes = coreInstBytes * fetchWidth
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val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
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TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = Seq(AddressSet(itimAddr, size-1)),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsPutFull = TransferSizes(1, wordBytes),
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supportsGet = TransferSizes(1, wordBytes),
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fifoId = Some(0))), // requests handled in FIFO order
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beatBytes = wordBytes,
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minLatency = 1)))
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}
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}
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class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val req = Valid(new ICacheReq).flip
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val hartid = UInt(INPUT, p(XLen))
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val req = Decoupled(new ICacheReq).flip
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val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
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val s2_vaddr = UInt(INPUT, vaddrBits) // delayed two cycles w.r.t. req
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val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
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val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
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val resp = Valid(UInt(width = coreInstBits * fetchWidth))
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val invalidate = Bool(INPUT)
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val mem = outer.node.bundleOut
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val tl_out = outer.node.bundleOut
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val tl_in = outer.slaveNode.map(_.bundleIn)
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}
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// get a tile-specific property without breaking deduplication
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object GetPropertyByHartId {
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def apply[T <: Data](tiles: Seq[RocketTileParams], f: RocketTileParams => Option[T], hartId: UInt): T = {
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PriorityMux(tiles.zipWithIndex.collect { case (t, i) if f(t).nonEmpty => (hartId === i) -> f(t).get })
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}
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}
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class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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with HasL1ICacheParameters {
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val io = new ICacheBundle(outer)
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val edge = outer.node.edgesOut(0)
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val tl_out = io.mem(0)
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val edge_out = outer.node.edgesOut.head
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val tl_out = io.tl_out.head
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val edge_in = outer.slaveNode.map(_.edgesIn.head)
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val tl_in = io.tl_in.map(_.head)
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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require(!usingVM || pgIdxBits >= untagBits)
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val scratchpadOn = RegInit(false.B)
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val scratchpadMax = Reg(UInt(width = log2Ceil(nSets * (nWays - 1))))
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def lineInScratchpad(line: UInt) = scratchpadOn && line <= scratchpadMax
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def addrMaybeInScratchpad(addr: UInt) = if (outer.icacheParams.itimAddr.isEmpty) false.B else {
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val base = GetPropertyByHartId(p(coreplex.RocketTilesKey), _.icache.flatMap(_.itimAddr.map(_.U)), io.hartid)
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val size = nSets * nWays * cacheBlockBytes
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addr >= base && addr < base + size
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}
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def addrInScratchpad(addr: UInt) = addrMaybeInScratchpad(addr) && lineInScratchpad(addr(untagBits+log2Ceil(nWays)-1, blockOffBits))
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def scratchpadWay(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, untagBits)
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def scratchpadWayValid(way: UInt) = way < nWays - 1
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def scratchpadLine(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, blockOffBits)
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val s0_slaveValid = tl_in.map(_.a.fire()).getOrElse(false.B)
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val s1_slaveValid = RegNext(s0_slaveValid, false.B)
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val s2_slaveValid = RegNext(s1_slaveValid, false.B)
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val s3_slaveValid = RegNext(s2_slaveValid, false.B)
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val s_ready :: s_request :: s_refill :: Nil = Enum(UInt(), 3)
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val state = Reg(init=s_ready)
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val invalidated = Reg(Bool())
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val refill_addr = Reg(UInt(width = paddrBits))
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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val refill_idx = refill_addr(untagBits-1,blockOffBits)
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val s1_tag_hit = Wire(Vec(nWays, Bool()))
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val s1_any_tag_hit = s1_tag_hit.reduce(_||_)
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val s1_any_tag_hit = s1_tag_hit.reduce(_||_) || Mux(s1_slaveValid, true.B, addrMaybeInScratchpad(io.s1_paddr))
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val s1_valid = Reg(init=Bool(false))
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val out_valid = s1_valid && state === s_ready && !io.s1_kill
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val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
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val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
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val s1_hit = out_valid && s1_any_tag_hit
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val s1_hit = s1_valid && s1_any_tag_hit
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val s1_miss = s1_valid && state === s_ready && !s1_any_tag_hit
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val s0_valid = io.req.valid && state === s_ready
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io.req.ready := !(tl_out.d.fire() || s0_slaveValid || s3_slaveValid)
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val s0_valid = io.req.fire()
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val s0_vaddr = io.req.bits.addr
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s1_valid := s0_valid
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when (s1_miss) { refill_addr := io.s1_paddr }
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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val refill_idx = refill_addr(untagBits-1,blockOffBits)
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val (_, _, refill_done, refill_cnt) = edge.count(tl_out.d)
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tl_out.d.ready := Bool(true)
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require (edge.manager.minLatency > 0)
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val (_, _, refill_done, refill_cnt) = edge_out.count(tl_out.d)
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tl_out.d.ready := !s3_slaveValid
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require (edge_out.manager.minLatency > 0)
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val repl_way = if (isDM) UInt(0) else {
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// pick a way that is not used by the scratchpad
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val v0 = LFSR16(tl_out.a.fire())(log2Up(nWays)-1,0)
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var v = v0
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for (i <- log2Ceil(nWays) - 1 to 0 by -1) {
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val mask = nWays - (BigInt(1) << (i + 1))
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v = v | (lineInScratchpad(Cat(v0 | mask.U, refill_idx)) << i)
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}
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assert(!lineInScratchpad(Cat(v, refill_idx)))
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v
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}
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val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
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val entagbits = code.width(tagBits)
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val tag_array = SeqMem(nSets, Vec(nWays, Bits(width = entagbits)))
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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@ -99,8 +150,9 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (refill_done && !invalidated) {
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vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), Bool(true))
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when (tl_out.d.fire()) {
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// clear bit when refill starts so hit-under-miss doesn't fetch bad data
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vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
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}
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val invalidate = Wire(init = io.invalidate)
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when (invalidate) {
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@ -108,75 +160,130 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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invalidated := Bool(true)
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}
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val s0_slaveAddr = tl_in.map(_.a.bits.address).getOrElse(0.U)
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val s1s3_slaveAddr = Reg(UInt())
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val s1s3_slaveData = Reg(UInt())
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val s1_tag_disparity = Wire(Vec(nWays, Bool()))
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val wordBits = coreInstBits * fetchWidth
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val s1_dout = Wire(Vec(nWays, UInt(width = code.width(wordBits))))
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val s1_dout_valid = RegNext(s0_valid)
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for (i <- 0 until nWays) {
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val s1_vb = vb_array(Cat(UInt(i), io.s1_paddr(untagBits-1,blockOffBits))).toBool
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s1_tag_disparity(i) := code.decode(tag_rdata(i)).error
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s1_tag_hit(i) := s1_vb && code.decode(tag_rdata(i)).uncorrected === s1_tag
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val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
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val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
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val scratchpadHit = Bool(i < nWays-1) &&
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Mux(s1_slaveValid,
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lineInScratchpad(scratchpadLine(s1s3_slaveAddr)) && scratchpadWay(s1s3_slaveAddr) === i,
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addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i)
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val s1_vb = vb_array(Cat(UInt(i), s1_idx)) && !s1_slaveValid
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s1_tag_disparity(i) := s1_vb && code.decode(tag_rdata(i)).error
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s1_tag_hit(i) := scratchpadHit || (s1_vb && code.decode(tag_rdata(i)).uncorrected === s1_tag)
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}
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assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1)
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require(rowBits % wordBits == 0)
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val data_arrays = Seq.fill(rowBits / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = code.width(wordBits)))) }
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require(tl_out.d.bits.data.getWidth % wordBits == 0)
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val data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = code.width(wordBits)))) }
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for ((data_array, i) <- data_arrays zipWithIndex) {
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val wen = tl_out.d.valid
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
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def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
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val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))
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val wen = (tl_out.d.fire() && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr))
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val mem_idx = Mux(tl_out.d.fire(), (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
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Mux(s3_slaveValid, row(s1s3_slaveAddr),
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Mux(s0_slaveValid, row(s0_slaveAddr),
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row(s0_vaddr))))
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when (wen) {
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val idx = (refill_idx << log2Ceil(refillCycles)) | refill_cnt
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val data = tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i)
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data_array.write(idx, Vec.fill(nWays)(code.encode(data)), (0 until nWays).map(repl_way === _))
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val data = Mux(s3_slaveValid, s1s3_slaveData, tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i))
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val way = Mux(s3_slaveValid, scratchpadWay(s1s3_slaveAddr), repl_way)
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data_array.write(mem_idx, Vec.fill(nWays)(code.encode(data)), (0 until nWays).map(way === _))
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}
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(rowBytes)-1, log2Ceil(wordBits/8)) === i
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val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
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val dout = data_array.read(s0_raddr, !wen && (s0_valid && wordMatch(s0_vaddr)))
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when (wordMatch(io.s1_paddr)) {
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val dout = data_array.read(mem_idx, !wen && s0_ren)
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when (wordMatch(Mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr))) {
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s1_dout := dout
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}
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}
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/*
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for ((data_array, i) <- data_arrays zipWithIndex) {
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val wen = tl_out.d.valid && repl_way === UInt(i)
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when (wen) {
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val e_d = code.encode(tl_out.d.bits.data)
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data_array.write((refill_idx << log2Ceil(refillCycles)) | refill_cnt, e_d)
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}
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val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
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s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid)
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}
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*/
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// output signals
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outer.latency match {
|
||||
case 1 =>
|
||||
require(code.width(rowBits) == rowBits) // no ECC
|
||||
require(code.isInstanceOf[uncore.util.IdentityCode])
|
||||
require(outer.icacheParams.itimAddr.isEmpty)
|
||||
io.resp.bits := Mux1H(s1_tag_hit, s1_dout)
|
||||
io.resp.valid := s1_hit
|
||||
|
||||
case 2 =>
|
||||
val s2_valid = RegNext(out_valid, Bool(false))
|
||||
val s2_valid = RegNext(s1_valid && !io.s1_kill, Bool(false))
|
||||
val s2_hit = RegNext(s1_hit, Bool(false))
|
||||
val s2_tag_hit = RegEnable(s1_tag_hit, s1_valid)
|
||||
val s2_dout = RegEnable(s1_dout, s1_valid)
|
||||
val s2_tag_hit = RegEnable(s1_tag_hit, s1_valid || s1_slaveValid)
|
||||
val s2_dout = RegEnable(s1_dout, s1_valid || s1_slaveValid)
|
||||
val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
|
||||
|
||||
val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_valid).asUInt.orR
|
||||
val s2_data_disparity = code.decode(s2_way_mux).error
|
||||
val s2_disparity = s2_tag_disparity || s2_data_disparity
|
||||
val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_valid || s1_slaveValid).asUInt.orR
|
||||
val s2_data_decoded = code.decode(s2_way_mux)
|
||||
val s2_disparity = s2_tag_disparity || s2_data_decoded.error
|
||||
when (s2_valid && s2_disparity) { invalidate := true }
|
||||
|
||||
io.resp.bits := code.decode(s2_way_mux).uncorrected
|
||||
io.resp.bits := s2_data_decoded.uncorrected
|
||||
io.resp.valid := s2_hit && !s2_disparity
|
||||
|
||||
tl_in.map { tl =>
|
||||
tl.a.ready := !tl_out.d.fire() && !s1_slaveValid && !s2_slaveValid && !(tl.d.valid && !tl.d.ready)
|
||||
val s1_a = RegEnable(tl.a.bits, s0_slaveValid)
|
||||
when (s0_slaveValid) {
|
||||
val a = tl.a.bits
|
||||
s1s3_slaveAddr := tl.a.bits.address
|
||||
s1s3_slaveData := tl.a.bits.data
|
||||
when (edge_in.get.hasData(a)) {
|
||||
val enable = scratchpadWayValid(scratchpadWay(a.address))
|
||||
when (!lineInScratchpad(scratchpadLine(a.address))) {
|
||||
scratchpadMax := scratchpadLine(a.address)
|
||||
when (enable) { invalidate := true }
|
||||
}
|
||||
scratchpadOn := enable
|
||||
}
|
||||
}
|
||||
|
||||
assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)
|
||||
when (!(tl.a.valid || s1_slaveValid || s2_slaveValid)
|
||||
&& s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) {
|
||||
// handle correctable errors on CPU accesses to the scratchpad.
|
||||
// if there is an in-flight slave-port access to the scratchpad,
|
||||
// report the a miss but don't correct the error (as there is
|
||||
// a structural hazard on s1s3_slaveData/s1s3_slaveAddress).
|
||||
s3_slaveValid := true
|
||||
s1s3_slaveData := s2_data_decoded.corrected
|
||||
s1s3_slaveAddr := Cat(OHToUInt(s2_tag_hit), io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), s1s3_slaveAddr(log2Ceil(wordBits/8)-1, 0))
|
||||
}
|
||||
|
||||
val respValid = RegInit(false.B)
|
||||
respValid := s2_slaveValid || (respValid && !tl.d.ready)
|
||||
when (s2_slaveValid) {
|
||||
when (edge_in.get.hasData(s1_a)) { s3_slaveValid := true }
|
||||
def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))
|
||||
s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt
|
||||
}
|
||||
|
||||
tl.d.valid := respValid
|
||||
tl.d.bits := Mux(edge_in.get.hasData(s1_a),
|
||||
edge_in.get.AccessAck(s1_a, UInt(0)),
|
||||
edge_in.get.AccessAck(s1_a, UInt(0), UInt(0)))
|
||||
tl.d.bits.data := s1s3_slaveData
|
||||
|
||||
// Tie off unused channels
|
||||
tl.b.valid := false
|
||||
tl.c.ready := true
|
||||
tl.e.ready := true
|
||||
}
|
||||
}
|
||||
tl_out.a.valid := state === s_request && !io.s2_kill
|
||||
tl_out.a.bits := edge.Get(
|
||||
tl_out.a.bits := edge_out.Get(
|
||||
fromSource = UInt(0),
|
||||
toAddress = (refill_addr >> blockOffBits) << blockOffBits,
|
||||
lgSize = lgCacheBlockBytes)._2
|
||||
tl_out.b.ready := Bool(true)
|
||||
tl_out.c.valid := Bool(false)
|
||||
tl_out.e.valid := Bool(false)
|
||||
assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))
|
||||
|
||||
// control state machine
|
||||
switch (state) {
|
||||
|
||||
@ -8,8 +8,10 @@ import chisel3.core.withReset
|
||||
import config._
|
||||
import tile._
|
||||
import uncore.constants._
|
||||
import diplomacy._
|
||||
import util._
|
||||
import Chisel.ImplicitConversions._
|
||||
import collection.immutable.ListMap
|
||||
|
||||
case class RocketCoreParams(
|
||||
bootFreqHz: BigInt = 0,
|
||||
|
||||
@ -105,7 +105,7 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L
|
||||
}
|
||||
|
||||
/** Mix-ins for constructing tiles that have optional scratchpads */
|
||||
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
|
||||
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCoreParameters {
|
||||
val module: CanHaveScratchpadModule
|
||||
|
||||
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
|
||||
@ -113,6 +113,10 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
|
||||
val slaveNode = TLInputNode()
|
||||
|
||||
scratch foreach { lm => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(slaveNode) }
|
||||
frontend.slaveNode foreach { _ :=
|
||||
TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), true)(
|
||||
TLWidthWidget(p(XLen)/8)(slaveNode))
|
||||
}
|
||||
|
||||
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
|
||||
val finalNode = frontend.node.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
|
||||
|
||||
@ -132,6 +132,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
|
||||
core.io.hartid := io.hartid // Pass through the hartid
|
||||
outer.frontend.module.io.cpu <> core.io.imem
|
||||
outer.frontend.module.io.resetVector := io.resetVector
|
||||
outer.frontend.module.io.hartid := io.hartid
|
||||
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
|
||||
fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
|
||||
core.io.ptw <> ptw.io.dpath
|
||||
|
||||
Loading…
Reference in New Issue
Block a user