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Add Instruction Tightly Integrated Memory

This commit is contained in:
Andrew Waterman
2017-04-24 17:14:23 -07:00
parent ee6702e5e0
commit 418879a47f
5 changed files with 193 additions and 70 deletions

View File

@ -8,8 +8,10 @@ import chisel3.core.withReset
import config._
import tile._
import uncore.constants._
import diplomacy._
import util._
import Chisel.ImplicitConversions._
import collection.immutable.ListMap
case class RocketCoreParams(
bootFreqHz: BigInt = 0,