riscv/rocket-chip
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Add Instruction Tightly Integrated Memory

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This commit is contained in:
Andrew Waterman
2017-04-24 17:14:23 -07:00
parent ee6702e5e0
commit 418879a47f
5 changed files with 193 additions and 70 deletions
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29
src/main/scala/rocket/Frontend.scala
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@ -42,10 +42,15 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val acquire = Bool(INPUT)
}
class Frontend(implicit p: Parameters) extends LazyModule {
class Frontend(hartid: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new FrontendModule(this)
val icache = LazyModule(new ICache(latency = 2))
val icache = LazyModule(new ICache(latency = 2, hartid))
val node = TLOutputNode()
val slaveNode = icache.slaveNode.map { n =>
val res = TLInputNode()
n := res
res
}
node := icache.node
}
@ -53,8 +58,10 @@ class Frontend(implicit p: Parameters) extends LazyModule {
class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
val cpu = new FrontendIO().flip
val ptw = new TLBPTWIO()
val mem = outer.node.bundleOut
val tl_out = outer.node.bundleOut
val tl_in = outer.slaveNode.map(_.bundleIn)
val resetVector = UInt(INPUT, vaddrBitsExtended)
val hartid = UInt(INPUT, p(XLen))
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
@ -68,8 +75,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 3, flow = true)) }
val s0_valid = io.cpu.req.valid || fq.io.enq.ready
val s1_pc_ = Reg(UInt(width=vaddrBitsExtended))
val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
val s1_pc = Reg(UInt(width=vaddrBitsExtended))
val s1_speculative = Reg(Bool())
val s2_valid = Reg(init=Bool(true))
val s2_pc = Reg(init=io.resetVector)
@ -94,7 +100,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
s2_replay := (s2_valid && !fq.io.enq.fire()) || RegNext(s2_replay && !s0_valid)
val npc = Mux(s2_replay, s2_pc, predicted_npc)
s1_pc_ := io.cpu.npc
s1_pc := io.cpu.npc
// consider RVC fetches across blocks to be non-speculative if the first
// part was non-speculative
val s0_speculative =
@ -116,7 +122,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
if (usingBTB) {
val btb = Module(new BTB)
btb.io.req.valid := false
btb.io.req.bits.addr := s1_pc_
btb.io.req.bits.addr := s1_pc
btb.io.btb_update := io.cpu.btb_update
btb.io.bht_update := io.cpu.bht_update
btb.io.ras_update := io.cpu.ras_update
@ -148,16 +154,18 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
tlb.io.req.bits.sfence := io.cpu.sfence
tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)
icache.io.hartid := io.hartid
icache.io.req.valid := s0_valid
icache.io.req.bits.addr := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || s2_replay
icache.io.s2_kill := s2_speculative && !s2_cacheable || s2_xcpt
fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill)
fq.io.enq.bits.pc := s2_pc
io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
io.cpu.npc := ~(~Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) | (coreInstBytes-1)) // discard LSB(s)
fq.io.enq.bits.data := icache.io.resp.bits
fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
@ -170,13 +178,14 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
io.cpu.resp <> fq.io.deq
// performance events
io.cpu.acquire := edge.done(icache.io.mem(0).a)
io.cpu.acquire := edge.done(icache.io.tl_out(0).a)
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend)
val frontend = LazyModule(new Frontend(hartid: Int))
val hartid: Int
masterNode := frontend.node
nPTWPorts += 1
}