riscv/rocket-chip
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TLB: do not access illegal addresses (#460)

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Wesley W. Terpstra 2016-11-26 15:11:42 -08:00 committed by GitHub
parent 97a853a995
commit 4146f6a792
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/rocket/tlb.scala
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@ -65,8 +65,10 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0)
val do_refill = Bool(usingVM) && io.ptw.resp.valid
val mpu_ppn = Mux(do_refill, refill_ppn, passthrough_ppn)
val mpu_physaddr = mpu_ppn << pgIdxBits
val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_)
def fastCheck(member: TLManagerParameters => Boolean) =
Mux1H(edge.manager.findFast(mpu_ppn << pgIdxBits), edge.manager.managers.map(m => Bool(member(m))))
legal_address && Mux1H(edge.manager.findFast(mpu_physaddr), edge.manager.managers.map(m => Bool(member(m))))
val prot_r = fastCheck(_.supportsGet)
val prot_w = fastCheck(_.supportsPutFull)
val prot_x = fastCheck(_.executable)