rocketchip Periphery: ExtMem and ExtBus Configs

src/main/scala/groundtest/BusMasterTest.scala

@@ -6,6 +6,7 @@ import uncore.agents._
 import uncore.coherence.{InnerTLId, OuterTLId}
 import util._
 import junctions.HasAddrMapParameters
+import rocketchip._
 import cde.Parameters
 
 /**
@@ -20,7 +21,7 @@ class ExampleBusMaster(implicit val p: Parameters) extends Module
     with HasTileLinkParameters {
   val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
   val memParams = p.alterPartial({ case TLId => p(OuterTLId) })
-  val memStart = addrMap("mem").start
+  val memStart = p(ExtMemBase)
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
 
   val io = new Bundle {
@@ -69,7 +70,7 @@ class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
        s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
   val state = Reg(init = s_idle)
 
-  val busMasterBlock = addrMap("io:pbus:busmaster").start >> p(CacheBlockOffsetBits)
+  val busMasterBlock = p(ExtBusBase) >> p(CacheBlockOffsetBits)
   val start_acq = Put(
     client_xact_id = UInt(0),
     addr_block = UInt(busMasterBlock),

src/main/scala/groundtest/Configs.scala

@@ -93,7 +93,7 @@ class WithGroundTest extends Config(
     case BuildExampleTop =>
       (p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p))
     case FPUKey => None
-    case UseAtomics => true
+    case UseAtomics => false
     case UseCompressed => false
     case _ => throw new CDEMatchError
   })
@@ -137,7 +137,7 @@ class WithMemtest extends Config(
     }
     case GeneratorKey => TrafficGeneratorParameters(
       maxRequests = 128,
-      startAddress = site(GlobalAddrMap)("mem").start)
+      startAddress = BigInt(site(ExtMemBase)))
     case BuildGroundTest =>
       (p: Parameters) => Module(new GeneratorTest()(p))
     case _ => throw new CDEMatchError

src/main/scala/groundtest/Regression.scala

@@ -7,6 +7,7 @@ import uncore.agents._
 import util._
 import junctions.HasAddrMapParameters
 import rocket._
+import rocketchip._
 import cde.{Parameters, Field}
 
 class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
@@ -19,7 +20,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 
 abstract class Regression(implicit val p: Parameters)
     extends Module with HasTileLinkParameters with HasAddrMapParameters {
-  val memStart = addrMap("mem").start
+  val memStart = p(ExtMemBase)
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
   val io = new RegressionIO
 

src/main/scala/groundtest/Tile.scala

@@ -5,6 +5,7 @@ import rocket._
 import uncore.tilelink._
 import uncore.agents.CacheName
 import uncore.tilelink2._
+import rocketchip.ExtMemBase
 import diplomacy._
 import scala.util.Random
 import scala.collection.mutable.ListBuffer
@@ -23,13 +24,13 @@ trait HasGroundTestConstants {
   val errorCodeBits = 4
 }
 
-trait HasGroundTestParameters extends HasAddrMapParameters {
+trait HasGroundTestParameters {
   implicit val p: Parameters
   val tileSettings = p(GroundTestKey)(p(TileId))
   val nUncached = tileSettings.uncached
   val nCached = tileSettings.cached
   val nPTW = tileSettings.ptw
-  val memStart = addrMap("mem").start
+  val memStart = p(ExtMemBase)
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
 }
 

src/main/scala/rocketchip/Configs.scala

@@ -60,7 +60,10 @@ class BasePlatformConfig extends Config(
         case AsyncMemChannels => false
         case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
         case TMemoryChannels => BusType.AXI
+        case ExtMemBase => Dump("MEM_BASE", 0x80000000L)
         case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
+        case ExtBusBase => 0x60000000L
+        case ExtBusSize => 0x20000000L
         case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
         case SimMemLatency => 0
         case _ => throw new CDEMatchError

src/main/scala/rocketchip/Periphery.scala

@@ -38,6 +38,9 @@ case object AsyncDebugBus extends Field[Boolean]
 case object AsyncMemChannels extends Field[Boolean]
 /** Specifies the size of external memory */
 case object ExtMemSize extends Field[Long]
+case object ExtMemBase extends Field[Long]
+case object ExtBusSize extends Field[Long]
+case object ExtBusBase extends Field[Long]
 /** Specifies the number of external interrupts */
 case object NExtTopInterrupts extends Field[Int]
 /** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra  **/
@@ -121,10 +124,9 @@ trait PeripheryExtInterruptsModule {
 trait PeripheryMasterAXI4Mem {
   this: BaseTop[BaseCoreplex] with TopNetwork =>
 
-  val base = 0x80000000L
+  val base = p(ExtMemBase)
   val size = p(ExtMemSize)
   val channels = coreplexMem.size
-  Dump("MEM_BASE", base)
 
   val mem_axi4 = coreplexMem.zipWithIndex.map { case (node, i) =>
     val c_size = size/channels
@@ -172,7 +174,7 @@ trait PeripheryMasterAXI4MMIO {
 
   val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
-      address       = List(AddressSet(0x60000000L, 0x1fffffffL)),
+      address       = List(AddressSet(p(ExtBusBase), p(ExtBusSize)-1)),
       executable    = true,                  // Can we run programs on this memory?
       supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
       supportsRead  = TransferSizes(1, 256),

src/main/scala/rocketchip/Utils.scala

@@ -89,14 +89,6 @@ object GenerateConfigString {
     val res = new StringBuilder
     res append plic.module.globalConfigString
     res append clint.module.globalConfigString
-    if (addrMap contains "mem") {
-      res append  "ram {\n"
-      res append  "  0 {\n"
-      res append s"    addr 0x${addrMap("mem").start.toString(16)};\n"
-      res append s"    size 0x${addrMap("mem").size.toString(16)};\n"
-      res append  "  };\n"
-      res append  "};\n"
-    }
     res append  "core {\n"
     for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
       val isa = {