riscv/rocket-chip
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rocketchip Periphery: ExtMem and ExtBus Configs

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This commit is contained in:
Henry Cook
2016-11-16 16:16:08 -08:00
parent 1f51564577
commit 408e78e35e
7 changed files with 18 additions and 18 deletions
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3
src/main/scala/rocketchip/Configs.scala
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@ -60,7 +60,10 @@ class BasePlatformConfig extends Config(
case AsyncMemChannels => false
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case TMemoryChannels => BusType.AXI
case ExtMemBase => Dump("MEM_BASE", 0x80000000L)
case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
case ExtBusBase => 0x60000000L
case ExtBusSize => 0x20000000L
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case SimMemLatency => 0
case _ => throw new CDEMatchError

8
src/main/scala/rocketchip/Periphery.scala
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@ -38,6 +38,9 @@ case object AsyncDebugBus extends Field[Boolean]
case object AsyncMemChannels extends Field[Boolean]
/** Specifies the size of external memory */
case object ExtMemSize extends Field[Long]
case object ExtMemBase extends Field[Long]
case object ExtBusSize extends Field[Long]
case object ExtBusBase extends Field[Long]
/** Specifies the number of external interrupts */
case object NExtTopInterrupts extends Field[Int]
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
@ -121,10 +124,9 @@ trait PeripheryExtInterruptsModule {
trait PeripheryMasterAXI4Mem {
this: BaseTop[BaseCoreplex] with TopNetwork =>
val base = 0x80000000L
val base = p(ExtMemBase)
val size = p(ExtMemSize)
val channels = coreplexMem.size
Dump("MEM_BASE", base)
val mem_axi4 = coreplexMem.zipWithIndex.map { case (node, i) =>
val c_size = size/channels
@ -172,7 +174,7 @@ trait PeripheryMasterAXI4MMIO {
val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x60000000L, 0x1fffffffL)),
address = List(AddressSet(p(ExtBusBase), p(ExtBusSize)-1)),
executable = true, // Can we run programs on this memory?
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256),

8
src/main/scala/rocketchip/Utils.scala
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@ -89,14 +89,6 @@ object GenerateConfigString {
val res = new StringBuilder
res append plic.module.globalConfigString
res append clint.module.globalConfigString
if (addrMap contains "mem") {
res append "ram {\n"
res append " 0 {\n"
res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
res append s" size 0x${addrMap("mem").size.toString(16)};\n"
res append " };\n"
res append "};\n"
}
res append "core {\n"
for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
val isa = {