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rocketchip Periphery: ExtMem and ExtBus Configs

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This commit is contained in:
Henry Cook
2016-11-16 16:16:08 -08:00
parent 1f51564577
commit 408e78e35e
7 changed files with 18 additions and 18 deletions
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5
src/main/scala/groundtest/Tile.scala
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@ -5,6 +5,7 @@ import rocket._
import uncore.tilelink._
import uncore.agents.CacheName
import uncore.tilelink2._
import rocketchip.ExtMemBase
import diplomacy._
import scala.util.Random
import scala.collection.mutable.ListBuffer
@ -23,13 +24,13 @@ trait HasGroundTestConstants {
val errorCodeBits = 4
}
trait HasGroundTestParameters extends HasAddrMapParameters {
trait HasGroundTestParameters {
implicit val p: Parameters
val tileSettings = p(GroundTestKey)(p(TileId))
val nUncached = tileSettings.uncached
val nCached = tileSettings.cached
val nPTW = tileSettings.ptw
val memStart = addrMap("mem").start
val memStart = p(ExtMemBase)
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
}