rocketchip Periphery: ExtMem and ExtBus Configs

src/main/scala/groundtest/BusMasterTest.scala

@@ -6,6 +6,7 @@ import uncore.agents._
 import uncore.coherence.{InnerTLId, OuterTLId}
 import util._
 import junctions.HasAddrMapParameters
+import rocketchip._
 import cde.Parameters
 
 /**
@@ -20,7 +21,7 @@ class ExampleBusMaster(implicit val p: Parameters) extends Module
     with HasTileLinkParameters {
   val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
   val memParams = p.alterPartial({ case TLId => p(OuterTLId) })
-  val memStart = addrMap("mem").start
+  val memStart = p(ExtMemBase)
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
 
   val io = new Bundle {
@@ -69,7 +70,7 @@ class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
        s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
   val state = Reg(init = s_idle)
 
-  val busMasterBlock = addrMap("io:pbus:busmaster").start >> p(CacheBlockOffsetBits)
+  val busMasterBlock = p(ExtBusBase) >> p(CacheBlockOffsetBits)
   val start_acq = Put(
     client_xact_id = UInt(0),
     addr_block = UInt(busMasterBlock),

src/main/scala/groundtest/Configs.scala

@@ -93,7 +93,7 @@ class WithGroundTest extends Config(
     case BuildExampleTop =>
       (p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p))
     case FPUKey => None
-    case UseAtomics => true
+    case UseAtomics => false
     case UseCompressed => false
     case _ => throw new CDEMatchError
   })
@@ -137,7 +137,7 @@ class WithMemtest extends Config(
     }
     case GeneratorKey => TrafficGeneratorParameters(
       maxRequests = 128,
-      startAddress = site(GlobalAddrMap)("mem").start)
+      startAddress = BigInt(site(ExtMemBase)))
     case BuildGroundTest =>
       (p: Parameters) => Module(new GeneratorTest()(p))
     case _ => throw new CDEMatchError

src/main/scala/groundtest/Regression.scala

@@ -7,6 +7,7 @@ import uncore.agents._
 import util._
 import junctions.HasAddrMapParameters
 import rocket._
+import rocketchip._
 import cde.{Parameters, Field}
 
 class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
@@ -19,7 +20,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 
 abstract class Regression(implicit val p: Parameters)
     extends Module with HasTileLinkParameters with HasAddrMapParameters {
-  val memStart = addrMap("mem").start
+  val memStart = p(ExtMemBase)
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
   val io = new RegressionIO
 

src/main/scala/groundtest/Tile.scala

@@ -5,6 +5,7 @@ import rocket._
 import uncore.tilelink._
 import uncore.agents.CacheName
 import uncore.tilelink2._
+import rocketchip.ExtMemBase
 import diplomacy._
 import scala.util.Random
 import scala.collection.mutable.ListBuffer
@@ -23,13 +24,13 @@ trait HasGroundTestConstants {
   val errorCodeBits = 4
 }
 
-trait HasGroundTestParameters extends HasAddrMapParameters {
+trait HasGroundTestParameters {
   implicit val p: Parameters
   val tileSettings = p(GroundTestKey)(p(TileId))
   val nUncached = tileSettings.uncached
   val nCached = tileSettings.cached
   val nPTW = tileSettings.ptw
-  val memStart = addrMap("mem").start
+  val memStart = p(ExtMemBase)
   val memStartBlock = memStart >> p(CacheBlockOffsetBits)
 }