From 407bc95c42624cde0b3c5151fd5725fd2c9ba361 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Fri, 15 Jul 2016 15:40:17 -0700
Subject: [PATCH] Rename MulDivUnroll to MulUnroll

---
 rocket                       | 2 +-
 src/main/scala/Configs.scala | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/rocket b/rocket
index c521632f..bb236036 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit c521632f6415cc703fdd8212f157f8ac9810d352
+Subproject commit bb23603632cead924cab2f00418668026173da6a
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index e51440d1..070cbbdf 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -195,7 +195,7 @@ class BaseConfig extends Config (
       case UsePerfCounters => true
       case FastLoadWord => true
       case FastLoadByte => false
-      case MulDivUnroll => 8
+      case MulUnroll => 8
       case DivEarlyOut => true
       case XLen => 64
       case UseFPU => {
@@ -445,7 +445,7 @@ class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
 class WithSmallCores extends Config (
     topDefinitions = { (pname,site,here) => pname match {
       case UseFPU => false
-      case MulDivUnroll => 1
+      case MulUnroll => 1
       case DivEarlyOut => false  
       case NTLBEntries => 4
       case BtbKey => BtbParameters(nEntries = 0)