From 402907990c2b05f70eb87f4847deca1e73d60b8d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 7 Aug 2017 17:33:20 -0700 Subject: [PATCH] Revert "Remove one gate from D$ ECC check" This reverts commit 7d94074b05a91403dca88fb2f4195174d3f69f29, which works fine with optimistic behavioral RAMs but not real ones. --- src/main/scala/rocket/DCache.scala | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 85073c64..e83796ea 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -232,10 +232,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) - val s2_data_error = { - val word_errors = s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq - needsRead(s2_req) && (if (usingDataScratchpad) word_errors(s2_word_idx) else word_errors.reduce(_||_)) - } + val s2_data_error = needsRead(s2_req) && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx) val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && !s2_meta_error && s2_hit