riscv/rocket-chip
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Hierarchicalize FPU and MulDiv parameters

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This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
This commit is contained in:
Andrew Waterman
2016-08-17 00:57:35 -07:00
committed by Howard Mao
parent fee5d2b1ea
commit 3f8c60bbd6
11 changed files with 61 additions and 79 deletions
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2
src/main/scala/Configs.scala
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@ -69,7 +69,7 @@ class BasePlatformConfig extends Config (
res append "};\n"
res append "core {\n"
for (i <- 0 until site(NTiles)) {
val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(UseFPU)) "fd" else ""}"
val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(FPUKey).nonEmpty) "fd" else ""}"
res append s" $i {\n"
res append " 0 {\n"
res append s" isa $isa;\n"

5
src/main/scala/TestConfigs.scala
View File

@ -30,7 +30,7 @@ class WithUnitTest extends Config(
case UnitTests => (testParams: Parameters) =>
JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
case NMemoryChannels => Dump("N_MEM_CHANNELS", 0)
case UseFPU => false
case FPUKey => None
case UseAtomics => false
case UseCompressed => false
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
@ -78,7 +78,7 @@ class WithGroundTest extends Config(
}
}
}
case UseFPU => false
case FPUKey => None
case UseAtomics => false
case UseCompressed => false
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
@ -199,6 +199,7 @@ class WithBusMasterTest extends Config(
}
Seq(new BusMasterDevice)
}
case _ => throw new CDEMatchError
})
class BusMasterTestConfig extends Config(new WithBusMasterTest ++ new GroundTestConfig)