riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Hierarchicalize FPU and MulDiv parameters

Browse Source 
This gets some leaf-level parameters out of the global parameterization,
better separating concerns.  This commit also allows disabling the
M extension.
This commit is contained in:
Andrew Waterman
2016-08-17 00:57:35 -07:00
committed by Howard Mao
parent fee5d2b1ea
commit 3f8c60bbd6
11 changed files with 61 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/tile.scala
View File

@ -56,7 +56,7 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
core.io.prci <> io.prci
icache.io.cpu <> core.io.imem
val fpuOpt = if (p(UseFPU)) Some(Module(new FPU)) else None
val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)))
fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
if (usingRocc) {
@ -127,7 +127,7 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
dcArb.io.requestor <> dcPorts
dcache.cpu <> dcArb.io.mem
if (!usingRocc || nFPUPorts == 0) {
if (nFPUPorts == 0) {
fpuOpt.foreach { fpu =>
fpu.io.cp_req.valid := Bool(false)
fpu.io.cp_resp.ready := Bool(false)