riscv/rocket-chip
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rocket: dtim is not a dcache

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Wesley W. Terpstra 2017-06-28 14:15:05 -07:00
parent bca3db0866
commit 3f6d5110cd
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/RocketTiles.scala
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@ -42,7 +42,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
val c = if (rocketParams.core.useCompressed) "c" else "" val c = if (rocketParams.core.useCompressed) "c" else ""
val isa = s"rv${p(XLen)}i$m$a$f$d$c" val isa = s"rv${p(XLen)}i$m$a$f$d$c"
val dcache = rocketParams.dcache.map(d => Map( val dcache = rocketParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
"d-cache-block-size" -> ofInt(block), "d-cache-block-size" -> ofInt(block),
"d-cache-sets" -> ofInt(d.nSets), "d-cache-sets" -> ofInt(d.nSets),
"d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map()) "d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())