riscv/rocket-chip
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subsystem: new bus attachment api

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This commit is contained in:
Henry Cook
2018-02-15 14:01:49 -08:00
parent 8462ea3d5b
commit 3f436a7612
17 changed files with 324 additions and 252 deletions
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47
src/main/scala/subsystem/Ports.scala
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@ -49,13 +49,10 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
beatBytes = params.beatBytes)
})
val converter = LazyModule(new TLToAXI4())
val trim = LazyModule(new AXI4IdIndexer(params.idBits))
val yank = LazyModule(new AXI4UserYanker)
val buffer = LazyModule(new AXI4Buffer)
memBuses.map(_.toDRAMController).foreach { case node =>
mem_axi4 := buffer.node := yank.node := trim.node := converter.node := node
memBuses.map { m =>
mem_axi4 := m.toDRAMController(Some("AXI4DRAM")) {
(AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
}
}
}
@ -93,13 +90,13 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
supportsRead = TransferSizes(1, params.maxXferBytes))),
beatBytes = params.beatBytes)))
(mmio_axi4
:= AXI4Buffer()
:= AXI4UserYanker()
:= AXI4Deinterleaver(sbus.blockBytes)
:= AXI4IdIndexer(params.idBits)
:= TLToAXI4()
:= sbus.toFixedWidthPorts)
mmio_axi4 := sbus.toFixedWidthPort(Some("AXI4MMIO")) {
(AXI4Buffer()
:= AXI4UserYanker()
:= AXI4Deinterleaver(sbus.blockBytes)
:= AXI4IdIndexer(params.idBits)
:= TLToAXI4())
}
}
/** Common io name and methods for propagating or tying off the port bundle */
@ -128,13 +125,13 @@ trait HasSlaveAXI4Port extends HasSystemBus {
id = IdRange(0, 1 << params.idBits))))))
private val fifoBits = 1
(sbus.fromSyncPorts()
:= TLWidthWidget(params.beatBytes)
:= AXI4ToTL()
:= AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))
:= AXI4Fragmenter()
:= AXI4IdIndexer(fifoBits)
:= l2FrontendAXI4Node)
sbus.fromPort(Some("AXI4Front")) {
(TLWidthWidget(params.beatBytes)
:= AXI4ToTL()
:= AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))
:= AXI4Fragmenter()
:= AXI4IdIndexer(fifoBits))
} := l2FrontendAXI4Node
}
/** Common io name and methods for propagating or tying off the port bundle */
@ -173,7 +170,9 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
supportsPutPartial = TransferSizes(1, sbus.blockBytes))),
beatBytes = params.beatBytes)))
mmio_tl := TLBuffer() := TLSourceShrinker(1 << params.idBits) := sbus.toFixedWidthPorts
mmio_tl := sbus.toFixedWidthPort(Some("TLMMIO")) {
TLBuffer() := TLSourceShrinker(1 << params.idBits)
}
}
/** Common io name and methods for propagating or tying off the port bundle */
@ -208,7 +207,9 @@ trait HasSlaveTLPort extends HasSystemBus {
name = "Front Port (TL)",
sourceId = IdRange(0, 1 << params.idBits))))))
sbus.fromSyncPorts() := TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes) := l2FrontendTLNode
sbus.fromPort(Some("TLFront")) {
TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes)
} := l2FrontendTLNode
}
/** Common io name and methods for propagating or tying off the port bundle */