riscv/rocket-chip
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subsystem: new bus attachment api

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Henry Cook committed 2018-02-21 14:43:47 -08:00
1 parent 8462ea3d5b
commit 3f436a7612
17 files changed
+324 -252
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src/main/scala/devices/tilelink/Plic.scala
+2 -2
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@@ -270,7 +270,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
/** Trait that will connect a PLIC to a subsystem */
trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
plic.node := pbus.toVariableWidthSlaves
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes)))
pbus.toVariableWidthSlave(Some("PLIC")) { plic.node }
plic.intnode := ibus.toPLIC
}