subsystem: new bus attachment api

src/main/scala/devices/tilelink/BootROM.scala

@@ -71,7 +71,7 @@ trait HasPeripheryBootROM extends HasPeripheryBus {
 
   val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))
 
-  bootrom.node := pbus.toVariableWidthSlaves
+  pbus.toVariableWidthSlave(Some("BootROM")){ bootrom.node }
 }
 
 /** Subsystem will power-on running at 0x10040 (BootROM) */

src/main/scala/devices/tilelink/CLINT.scala

@@ -93,5 +93,5 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
 /** Trait that will connect a CLINT to a subsystem */
 trait HasPeripheryCLINT extends HasPeripheryBus {
   val clint = LazyModule(new CLINT(p(CLINTKey), pbus.beatBytes))
-  clint.node := pbus.toVariableWidthSlaves
+  pbus.toVariableWidthSlave(Some("CLINT")) { clint.node }
 }

src/main/scala/devices/tilelink/Error.scala

@@ -121,6 +121,5 @@ class DeadlockDevice(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parame
 trait HasSystemErrorSlave extends HasSystemBus {
   private val params = p(ErrorParams)
   val error = LazyModule(new TLError(params, sbus.beatBytes))
-
-  error.node := sbus.toSlave
+  sbus.toSlave(Some("Error")){ error.node }
 }

src/main/scala/devices/tilelink/MaskROM.scala

@@ -17,7 +17,7 @@ trait HasPeripheryMaskROMSlave extends HasPeripheryBus {
   val maskROMParams = p(PeripheryMaskROMKey)
   val maskROMs = maskROMParams map { params =>
     val maskROM = LazyModule(new TLMaskROM(params))
-    maskROM.node := pbus.toFixedWidthSingleBeatSlave(maskROM.beatBytes)
+    pbus.toFixedWidthSingleBeatSlave(maskROM.beatBytes, Some("MaskROM")) { maskROM.node }
     maskROM
   }
 }

src/main/scala/devices/tilelink/Plic.scala

@@ -270,7 +270,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
 
 /** Trait that will connect a PLIC to a subsystem */
 trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
-  val plic  = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
-  plic.node := pbus.toVariableWidthSlaves
+  val plic  = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes)))
+  pbus.toVariableWidthSlave(Some("PLIC")) { plic.node }
   plic.intnode := ibus.toPLIC
 }

src/main/scala/devices/tilelink/Zero.scala

@@ -50,13 +50,16 @@ trait HasMemoryZeroSlave extends HasMemoryBus {
   private val params = p(ZeroParams)
   private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
 
-  val zeros = memBuses.map(_.toVariableWidthSlave).zipWithIndex.map { case (node, channel) =>
+  val zeros = memBuses
+                .map(m => m.toVariableWidthSlave(Some("Zero"))(_))
+                .zipWithIndex
+                .map { case (attach, channel) =>
     val channels = memBuses.size
     val base = AddressSet(params.base, params.size-1)
     val filter = AddressSet(channel * cacheBlockBytes, ~((channels-1) * cacheBlockBytes))
     val address = base.intersect(filter).get
     val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
-    zero.node := node
+    attach { zero.node }
     zero
   }
 }