Instantiate PTW unconditionally

This keeps the PMP datapaths intact.  The PTW itself will get optimized
away for the !usingVM case.

riscv-tools

@@ -1 +1 @@
-Subproject commit e15160d13aca4c007bcab70375eb438d7a204562
+Subproject commit 24ce6c0870755bd2af1bc39887ab84684c5ce586

src/main/scala/rocket/PTW.scala

@@ -205,6 +205,7 @@ trait CanHavePTW extends HasHellaCache {
 trait CanHavePTWModule extends HasHellaCacheModule {
   val outer: CanHavePTW
   val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
-  val ptwOpt = if (outer.usingPTW) { Some(Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edgesOut(0), outer.p))) } else None
-  ptwOpt foreach { ptw => dcachePorts += ptw.io.mem }
+  val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edgesOut(0), outer.p))
+  if (outer.usingPTW)
+    dcachePorts += ptw.io.mem
 }

src/main/scala/rocket/Tile.scala

@@ -125,7 +125,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
   outer.frontend.module.io.resetVector := io.resetVector
   dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
   fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
-  ptwOpt foreach { ptw => core.io.ptw <> ptw.io.dpath }
+  core.io.ptw <> ptw.io.dpath
   outer.legacyRocc foreach { lr =>
     lr.module.io.core.cmd <> core.io.rocc.cmd
     lr.module.io.core.exception := core.io.rocc.exception
@@ -149,7 +149,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
   require(h == o, s"port list size was $h, outer counted $o")
   // TODO figure out how to move the below into their respective mix-ins
   dcacheArb.io.requestor <> dcachePorts
-  ptwOpt foreach { ptw => ptw.io.requestor <> ptwPorts }
+  ptw.io.requestor <> ptwPorts
 }
 
 class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends LazyModule {