riscv/rocket-chip
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Instantiate PTW unconditionally

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This keeps the PMP datapaths intact.  The PTW itself will get optimized
away for the !usingVM case.
This commit is contained in:
Andrew Waterman
2017-03-24 13:00:47 -07:00
parent 30415215b8
commit 3f0d2fe826
3 changed files with 6 additions and 5 deletions
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5
src/main/scala/rocket/PTW.scala
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@ -205,6 +205,7 @@ trait CanHavePTW extends HasHellaCache {
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptwOpt = if (outer.usingPTW) { Some(Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edgesOut(0), outer.p))) } else None
ptwOpt foreach { ptw => dcachePorts += ptw.io.mem }
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edgesOut(0), outer.p))
if (outer.usingPTW)
dcachePorts += ptw.io.mem
}