diff --git a/src/main/scala/util/ShiftQueue.scala b/src/main/scala/util/ShiftQueue.scala
index 5914da89..d2baa988 100644
--- a/src/main/scala/util/ShiftQueue.scala
+++ b/src/main/scala/util/ShiftQueue.scala
@@ -26,7 +26,7 @@ class ShiftQueue[T <: Data](gen: T,
     val wdata = if (i == entries-1) io.enq.bits else Mux(valid(i+1), elts(i+1), io.enq.bits)
     val wen =
       Mux(io.deq.ready,
-          paddedValid(i+1) || io.enq.fire() && valid(i),
+          paddedValid(i+1) || io.enq.fire() && (Bool(i == 0 && !flow) || valid(i)),
           io.enq.fire() && paddedValid(i-1) && !valid(i))
     when (wen) { elts(i) := wdata }