From fa8844d5c3e573181726c39e0351372c345dfffd Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 28 Oct 2016 18:20:29 -0700 Subject: [PATCH 1/3] properly use rocket MT_ constants in regression tests --- src/main/scala/groundtest/Regression.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala index 650a9111..62b3e76e 100644 --- a/src/main/scala/groundtest/Regression.scala +++ b/src/main/scala/groundtest/Regression.scala @@ -6,7 +6,7 @@ import uncore.constants._ import uncore.agents._ import util._ import junctions.HasAddrMapParameters -import rocket.HellaCacheIO +import rocket._ import cde.{Parameters, Field} class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p) { @@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()( io.cache.req.valid := !get_sent && started io.cache.req.bits.addr := UInt(addrMap("io:pbus:TL2:bootrom").start) - io.cache.req.bits.typ := UInt(log2Ceil(32 / 8)) + io.cache.req.bits.typ := MT_WU io.cache.req.bits.cmd := M_XRD io.cache.req.bits.tag := UInt(0) io.cache.invalidate_lr := Bool(false) @@ -494,7 +494,7 @@ class ReleaseRegression(implicit p: Parameters) extends Regression()(p) { io.cache.req.valid := sending && state.isOneOf(s_write, s_read) io.cache.req.bits.addr := Cat(addr_blocks(req_idx), UInt(0, blockOffset)) - io.cache.req.bits.typ := UInt(log2Ceil(64 / 8)) + io.cache.req.bits.typ := MT_D io.cache.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD) io.cache.req.bits.tag := UInt(0) io.cache.req.bits.data := data(req_idx) @@ -625,7 +625,7 @@ class MergedPutRegression(implicit p: Parameters) extends Regression()(p) io.cache.req.valid := (state === s_cache_req) io.cache.req.bits.cmd := M_XWR - io.cache.req.bits.typ := UInt(log2Ceil(64 / 8)) + io.cache.req.bits.typ := MT_D io.cache.req.bits.addr := UInt(memStart) io.cache.req.bits.data := UInt(1) io.cache.req.bits.tag := UInt(0) From cb81ea516c9fde7b1db03ed69c8299a0ce8dc804 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 28 Oct 2016 18:20:47 -0700 Subject: [PATCH 2/3] add regression test for put-after-release bug --- src/main/scala/groundtest/Regression.scala | 51 +++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala index 62b3e76e..cf0fefe7 100644 --- a/src/main/scala/groundtest/Regression.scala +++ b/src/main/scala/groundtest/Regression.scala @@ -681,6 +681,54 @@ class MergedPutRegression(implicit p: Parameters) extends Regression()(p) io.errored := data_mismatch } +class PutAfterReleaseRegression(implicit p: Parameters) extends Regression()(p) { + val (s_idle :: s_cache_req :: s_cache_resp :: + s_write_first_req :: s_delay :: s_write_remaining_req :: s_write_resp :: + s_read_req :: s_read_resp :: s_finished :: Nil) = Enum(Bits(), 10) + val state = Reg(init = s_idle) + + val (delay_cnt, delay_done) = Counter(state === s_delay, 100) + val (write_cnt, write_done) = Counter( + io.mem.acquire.fire() && io.mem.acquire.bits.hasData(), tlDataBeats) + val (read_cnt, read_done) = Counter( + io.mem.grant.fire() && io.mem.grant.bits.hasData(), tlDataBeats) + + when (state === s_idle && io.start) { state := s_cache_req } + when (io.cache.req.fire()) { state := s_cache_resp } + when (state === s_cache_resp && io.cache.resp.valid) { state := s_write_first_req } + when (state === s_write_first_req && io.mem.acquire.ready) { state := s_delay } + when (delay_done) { state := s_write_remaining_req } + when (write_done) { state := s_write_resp } + when (state === s_write_resp && io.mem.grant.valid) { state := s_read_req } + when (state === s_read_req && io.mem.acquire.ready) { state := s_read_resp } + when (read_done) { state := s_finished } + + io.finished := state === s_finished + + io.cache.req.valid := state === s_cache_req + io.cache.req.bits.cmd := M_XWR + io.cache.req.bits.addr := UInt(memStart) + io.cache.req.bits.typ := MT_D + io.cache.req.bits.tag := UInt(0) + io.cache.req.bits.data := UInt(0) + + io.mem.acquire.valid := state.isOneOf(s_write_first_req, s_write_remaining_req, s_read_req) + io.mem.acquire.bits := Mux(state === s_read_req, + GetBlock( + client_xact_id = UInt(0), + addr_block = UInt(memStartBlock)), + PutBlock( + client_xact_id = UInt(0), + addr_block = UInt(memStartBlock), + addr_beat = write_cnt, + data = write_cnt + UInt(1))) + io.mem.grant.ready := state.isOneOf(s_write_resp, s_read_resp) + + assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() || + io.mem.grant.bits.data === read_cnt + UInt(1), + "PutAfterReleaseRegression: data mismatch") +} + object RegressionTests { def cacheRegressions(implicit p: Parameters) = Seq( Module(new PutBlockMergeRegression), @@ -699,7 +747,8 @@ object RegressionTests { Module(new IOGetAfterPutBlockRegression), Module(new WriteMaskedPutBlockRegression), Module(new PutBeforePutBlockRegression), - Module(new ReleaseRegression)) + Module(new ReleaseRegression), + Module(new PutAfterReleaseRegression)) } case object GroundTestRegressions extends Field[Parameters => Seq[Regression]] From f0e9a2a08184bd4fe0549d79d3de7ba9575dbf57 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 28 Oct 2016 18:23:50 -0700 Subject: [PATCH 3/3] Fix PutBlock after Release bug There is logic in the broadcast hub to skip the outer acquire if there is an outgoing release, since the data will be written out through the release channel. However, this will cause an issue in the case of PutBlock requests. If the tail beats of the PutBlock show up after the outer release has already been sent, the data will be corrupted. The fix is to make the outer release block if there are pending inner PutBlock beats. --- src/main/scala/uncore/agents/Broadcast.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/uncore/agents/Broadcast.scala b/src/main/scala/uncore/agents/Broadcast.scala index 53a7d780..6226b83e 100644 --- a/src/main/scala/uncore/agents/Broadcast.scala +++ b/src/main/scala/uncore/agents/Broadcast.scala @@ -175,6 +175,7 @@ class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters) // If there was a writeback, forward it outwards outerRelease( + block_orel = pending_put_data(vol_ognt_counter.up.idx), coh = outer_coh.onHit(M_XWR), data = data_buffer(vol_ognt_counter.up.idx))