This commit adds Logic & test support for JTAG implementation of Debug Transport Module.

- The DebugTransportModuleJtag is written in Verilog. It probably could be written in
  Chisel except for some negative edge clocking requirement.
- For real implementations, the AsyncDebugBusTo/From is insufficient. This commit
  includes cases where they are used, but because they are not reset asynchronously,
  a Verilog 'AsyncMailbox' is used when p(AsyncDebug) is false.
- This commit differs significantly from the earlier attempt. Now, the
  DTM and synchronizer is instantiated within Top, as it is a real piece of
  hardware (vs. test infrastructure).
-TestHarness takes a parameter vs. creating an entirely new TestHarness class.
It does not make sense to instantiate TestHarness when p(IncludeJtagDTM) is false,
and it would not make sense to insantiate some other TestHarness if p(IncludeJtagDTM)
is true.

To build Verilog which includes the JtagDTM within Top:

make CONFIG=WithJtagDTM_...

To test using gdb->OpenOCD->jtag_vpi->Verilog:

First, install openocd (included in this commit)

./bootstrap
./configure --prefix=$OPENOCD --enable-jtag-vpi
make
make install

Then to run a simulation:

On a 32-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-e300-sim \
  SimpleRegisterTest.test_s0

On a 64-bit core:

$(ROCKETCHIP)/riscv-tools/riscv-tests/debug/gdbserver.py \
  --run ./simv-TestHarness-WithJtagDTM_... \
  --cmd="$OPENOCD/bin/openocd --s $OPENOCD/share/openocd/scripts/" \
  --freedom-u500-sim \
  SimpleRegisterTest.test_s0

src/main/scala/rocketchip/TestHarness.scala

@@ -6,7 +6,6 @@ import Chisel._
 import cde.{Parameters, Field}
 import rocket.Util._
 import junctions._
-import uncore.devices.{IncludeJtagDTM} 
 
 class TestHarness(implicit p: Parameters) extends Module {
   val io = new Bundle {
@@ -53,16 +52,20 @@ class TestHarness(implicit p: Parameters) extends Module {
     dut.io.jtag.get.TRST := reset 
     jtag_vpi.io.enable := ~reset
     jtag_vpi.io.init_done := ~reset
+
+    // Success is determined by the gdbserver
+    // which is controlling this simulation.
     io.success := Bool(false)
   }
   else {
     val dtm = Module(new SimDTM)
     dut.io.debug.get <> dtm.io.debug
 
-    // Todo: enable the usage of different clocks.
-
+    // Todo: enable the usage of different clocks
+    // to test the synchronizer more aggressively.
     val dtm_clock = clock
     val dtm_reset = reset
+
     dtm.io.clk := dtm_clock
     dtm.io.reset := dtm_reset
     if (dut.io.debug_clk.isDefined)