riscv/rocket-chip
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Wesley W. Terpstra 2017-06-30 01:07:29 -07:00 committed by GitHub
parent e43b7accf9
commit 3dca2bc4a3
1 changed files with 1 additions and 1 deletions
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src/main/scala/uncore/devices/Plic.scala
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@ -180,7 +180,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
val claiming = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i), nDevices+1), UInt(0))}
val claimedDevs = Vec(claiming.reduceLeft( _ | _ ).toBools)
(pending zip gateways) zip claimedDevs) foreach { case ((p, g), c) =>
((pending zip gateways) zip claimedDevs) foreach { case ((p, g), c) =>
g.ready := !p
g.complete := false
when(c) {