From 3db066303b16f6ac6688cdc2f48d7ff066e4b52b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 31 Oct 2017 00:49:56 -0700 Subject: [PATCH] Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079) Workaround: disable interrupts and then do: .align 3 sb x0, (t0) # t0 contains ITIM-deallocate address fence.i --- src/main/scala/rocket/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index b2d90f1e..60db666b 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -225,7 +225,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr)) - val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr)) + val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr) && lineInScratchpad(scratchpadLine(s1s3_slaveAddr))) val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, Mux(s3_slaveValid, row(s1s3_slaveAddr), Mux(s0_slaveValid, row(s0_slaveAddr),