riscv/rocket-chip
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refactor NASTI to not use param; new AddrMap class

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This commit is contained in:
Henry Cook 2015-10-02 14:23:42 -07:00
parent c2ad0b7dd4
commit 3d10a89907
6 changed files with 70 additions and 69 deletions
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2
junctions

@ -1 +1 @@
Subproject commit 4145f066e8a528f033cf8ef27bcf16843061dd67 Subproject commit 52be2a2c019931de304c5701e694f243ef018e75

2
rocket

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Subproject commit ca26680973158727c4c7dcbff0d3054b988d5f7a Subproject commit 21285ad7a2e6697613b03eed97f18f83d2ec317a

37
src/main/scala/Configs.scala
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@ -15,15 +15,14 @@ class DefaultConfig extends ChiselConfig (
topDefinitions = { (pname,site,here) => topDefinitions = { (pname,site,here) =>
type PF = PartialFunction[Any,Any] type PF = PartialFunction[Any,Any]
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname) def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
def genCsrAddrMap() = { def genCsrAddrMap: AddrMap = {
val xLen = site(XLen) val csrSize = (1 << 12) * (site(XLen) / 8)
val nSCR = site(HTIFNSCR) val csrs = (0 until site(NTiles)).map{ i =>
val csrSize = (1 << 12) * (xLen / 8) AddrMapEntry(s"csr$i", None, MemSize(csrSize, AddrMapConsts.RW))
val nTiles = site(NTiles) }
val scrSize = site(HTIFNSCR) * (site(XLen) / 8)
(0 until nTiles) val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW))
.map(i => (s"csr$i", None, MemSize(csrSize, AddrMap.RW))) :+ new AddrMap(csrs :+ scr)
("scr", None, MemSize(nSCR * xLen / 8, AddrMap.RW))
} }
pname match { pname match {
// //
@ -50,9 +49,10 @@ class DefaultConfig extends ChiselConfig (
case MIFDataBits => Dump("MEM_DATA_BITS", 128) case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits)) case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits) case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
case NASTIDataBits => site(MIFDataBits) case NastiBitWidths => NastiParameters(
case NASTIAddrBits => site(PAddrBits) dataBits = site(MIFDataBits),
case NASTIIdBits => site(MIFTagBits) addrBits = site(PAddrBits),
idBits = site(MIFTagBits))
//Params used by all caches //Params used by all caches
case NSets => findBy(CacheName) case NSets => findBy(CacheName)
case NWays => findBy(CacheName) case NWays => findBy(CacheName)
@ -169,15 +169,10 @@ class DefaultConfig extends ChiselConfig (
case UseBackupMemoryPort => true case UseBackupMemoryPort => true
case MMIOBase => BigInt(1 << 30) // 1 GB case MMIOBase => BigInt(1 << 30) // 1 GB
case ExternalIOStart => 2 * site(MMIOBase) case ExternalIOStart => 2 * site(MMIOBase)
case NASTIAddrMap => Seq( case NastiAddrMap => AddrMap(
("mem", None, MemSize(site(MMIOBase), AddrMap.RWX)), AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)),
("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
genCsrAddrMap())), AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
("io", Some(site(ExternalIOStart)),
MemSize(2 * site(MMIOBase), AddrMap.RW)))
case NASTIAddrHashMap => new AddrHashMap(site(NASTIAddrMap))
case NASTINMasters => site(TLNManagers) + 1
case NASTINSlaves => site(NASTIAddrHashMap).nEntries
}}, }},
knobValues = { knobValues = {
case "NTILES" => 1 case "NTILES" => 1

85
src/main/scala/RocketChip.scala
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@ -31,19 +31,20 @@ case object ExternalIOStart extends Field[BigInt]
/** Utility trait for quick access to some relevant parameters */ /** Utility trait for quick access to some relevant parameters */
trait TopLevelParameters extends UsesParameters { trait TopLevelParameters extends UsesParameters {
val htifW = params(HTIFWidth) implicit val p: Parameters
val nTiles = params(NTiles) lazy val htifW = p(HTIFWidth)
val nMemChannels = params(NMemoryChannels) lazy val nTiles = p(NTiles)
val nBanksPerMemChannel = params(NBanksPerMemoryChannel) lazy val nMemChannels = p(NMemoryChannels)
val nBanks = nMemChannels*nBanksPerMemChannel lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
val lsb = params(BankIdLSB) lazy val nBanks = nMemChannels*nBanksPerMemChannel
val nMemReqs = params(NOutstandingMemReqsPerChannel) lazy val lsb = p(BankIdLSB)
val mifAddrBits = params(MIFAddrBits) lazy val nMemReqs = p(NOutstandingMemReqsPerChannel)
val mifDataBeats = params(MIFDataBeats) lazy val mifAddrBits = p(MIFAddrBits)
val scrAddrBits = log2Up(params(HTIFNSCR)) lazy val mifDataBeats = p(MIFDataBeats)
val pcrAddrBits = 12 lazy val scrAddrBits = log2Up(p(HTIFNSCR))
val xLen = params(XLen) lazy val pcrAddrBits = 12
require(lsb + log2Up(nBanks) < mifAddrBits) lazy val xLen = p(XLen)
//require(lsb + log2Up(nBanks) < mifAddrBits)
} }
class MemBackupCtrlIO extends Bundle { class MemBackupCtrlIO extends Bundle {
@ -63,19 +64,20 @@ class TopIO extends BasicTopIO {
val mem = new MemIO val mem = new MemIO
} }
class MultiChannelTopIO extends BasicTopIO with TopLevelParameters { class MultiChannelTopIO(implicit val p: Parameters) extends BasicTopIO with TopLevelParameters {
val mem = Vec(new NASTIIO, nMemChannels) val mem = Vec(new NastiIO, nMemChannels)
val mmio = new NASTIIO val mmio = new NastiIO
} }
/** Top-level module for the chip */ /** Top-level module for the chip */
//TODO: Remove this wrapper once multichannel DRAM controller is provided //TODO: Remove this wrapper once multichannel DRAM controller is provided
class Top extends Module with TopLevelParameters { class Top extends Module with TopLevelParameters {
implicit val p = params
val io = new TopIO val io = new TopIO
if(!params(UseZscale)) { if(!p(UseZscale)) {
val temp = Module(new MultiChannelTop) val temp = Module(new MultiChannelTop)
val arb = Module(new NASTIArbiter(nMemChannels)) val arb = Module(new NastiArbiter(nMemChannels))
val conv = Module(new MemIONASTIIOConverter(params(CacheBlockOffsetBits))) val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
arb.io.master <> temp.io.mem arb.io.master <> temp.io.mem
conv.io.nasti <> arb.io.slave conv.io.nasti <> arb.io.slave
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd) io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
@ -85,7 +87,7 @@ class Top extends Module with TopLevelParameters {
io.host <> temp.io.host io.host <> temp.io.host
// tie off the mmio port // tie off the mmio port
val errslave = Module(new NASTIErrorSlave) val errslave = Module(new NastiErrorSlave)
errslave.io <> temp.io.mmio errslave.io <> temp.io.mmio
} else { } else {
val temp = Module(new ZscaleTop) val temp = Module(new ZscaleTop)
@ -93,12 +95,13 @@ class Top extends Module with TopLevelParameters {
} }
} }
class MultiChannelTop extends Module with TopLevelParameters { class MultiChannelTop(implicit val p: Parameters) extends Module with TopLevelParameters {
val io = new MultiChannelTopIO val io = new MultiChannelTopIO
// Build an Uncore and a set of Tiles // Build an Uncore and a set of Tiles
val uncore = Module(new Uncore, {case TLId => "L1ToL2"}) val innerTLParams = p.alterPartial({case TLId => "L1ToL2" })
val tileList = uncore.io.htif zip params(BuildTiles) map { case(hl, bt) => bt(hl.reset) } val uncore = Module(new Uncore()(innerTLParams))(innerTLParams)
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset) }
// Connect each tile to the HTIF // Connect each tile to the HTIF
uncore.io.htif.zip(tileList).zipWithIndex.foreach { uncore.io.htif.zip(tileList).zipWithIndex.foreach {
@ -118,7 +121,7 @@ class MultiChannelTop extends Module with TopLevelParameters {
io.host <> uncore.io.host io.host <> uncore.io.host
io.mem <> uncore.io.mem io.mem <> uncore.io.mem
io.mmio <> uncore.io.mmio io.mmio <> uncore.io.mmio
if(params(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl } if(p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
} }
/** Wrapper around everything that isn't a Tile. /** Wrapper around everything that isn't a Tile.
@ -126,15 +129,15 @@ class MultiChannelTop extends Module with TopLevelParameters {
* Usually this is clocked and/or place-and-routed separately from the Tiles. * Usually this is clocked and/or place-and-routed separately from the Tiles.
* Contains the Host-Target InterFace module (HTIF). * Contains the Host-Target InterFace module (HTIF).
*/ */
class Uncore extends Module with TopLevelParameters { class Uncore(implicit val p: Parameters) extends Module with TopLevelParameters {
val io = new Bundle { val io = new Bundle {
val host = new HostIO val host = new HostIO
val mem = Vec(new NASTIIO, nMemChannels) val mem = Vec(new NastiIO, nMemChannels)
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val htif = Vec(new HTIFIO, nTiles).flip val htif = Vec(new HTIFIO, nTiles).flip
val mem_backup_ctrl = new MemBackupCtrlIO val mem_backup_ctrl = new MemBackupCtrlIO
val mmio = new NASTIIO val mmio = new NastiIO
} }
val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
@ -170,7 +173,7 @@ class Uncore extends Module with TopLevelParameters {
io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
io.mem <> outmemsys.io.mem io.mem <> outmemsys.io.mem
io.mmio <> outmemsys.io.mmio io.mmio <> outmemsys.io.mmio
if(params(UseBackupMemoryPort)) { if(p(UseBackupMemoryPort)) {
outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW) outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
@ -183,18 +186,18 @@ class Uncore extends Module with TopLevelParameters {
/** The whole outer memory hierarchy, including a NoC, some kind of coherence /** The whole outer memory hierarchy, including a NoC, some kind of coherence
* manager agent, and a converter from TileLink to MemIO. * manager agent, and a converter from TileLink to MemIO.
*/ */
class OuterMemorySystem extends Module with TopLevelParameters { class OuterMemorySystem(implicit val p: Parameters) extends Module with TopLevelParameters {
val io = new Bundle { val io = new Bundle {
val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
val htif_uncached = (new ClientUncachedTileLinkIO).flip val htif_uncached = (new ClientUncachedTileLinkIO).flip
val incoherent = Vec(Bool(), nTiles).asInput val incoherent = Vec(Bool(), nTiles).asInput
val mem = Vec(new NASTIIO, nMemChannels) val mem = Vec(new NastiIO, nMemChannels)
val mem_backup = new MemSerializedIO(htifW) val mem_backup = new MemSerializedIO(htifW)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles) val pcr = Vec(new SMIIO(xLen, pcrAddrBits), nTiles)
val scr = new SMIIO(xLen, scrAddrBits) val scr = new SMIIO(xLen, scrAddrBits)
val mmio = new NASTIIO val mmio = new NastiIO
} }
// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory // Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
@ -211,7 +214,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
// Create point(s) of coherence serialization // Create point(s) of coherence serialization
val nManagers = nMemChannels * nBanksPerMemChannel val nManagers = nMemChannels * nBanksPerMemChannel
val managerEndpoints = List.fill(nManagers) { params(BuildL2CoherenceManager)()} val managerEndpoints = List.fill(nManagers) { p(BuildL2CoherenceManager)()}
managerEndpoints.foreach { _.incoherent := io.incoherent } managerEndpoints.foreach { _.incoherent := io.incoherent }
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network, // Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
@ -220,21 +223,23 @@ class OuterMemorySystem extends Module with TopLevelParameters {
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) l1tol2net.io.managers <> managerEndpoints.map(_.innerTL)
// Create a converter between TileLinkIO and MemIO for each channel // Create a converter between TileLinkIO and MemIO for each channel
val outerTLParams = params.alterPartial({ case TLId => "L2ToMC" }) val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" })
val backendBuffering = TileLinkDepths(0,0,0,0,0) val backendBuffering = TileLinkDepths(0,0,0,0,0)
val addrMap = params(NASTIAddrHashMap) val addrMap = new AddrHashMap(p(NastiAddrMap))
val nMasters = managerEndpoints.size + 1
val nSlaves = addrMap.nEntries
println("Generated Address Map") println("Generated Address Map")
for ((name, base, size, _) <- addrMap.sortedEntries) { for ((name, base, size, _) <- addrMap.sortedEntries) {
println(f"\t$name%s $base%x - ${base + size - 1}%x") println(f"\t$name%s $base%x - ${base + size - 1}%x")
} }
val interconnect = Module(new NASTITopInterconnect) val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves)(p))
for ((bank, i) <- managerEndpoints.zipWithIndex) { for ((bank, i) <- managerEndpoints.zipWithIndex) {
val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams) val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
val conv = Module(new NASTIIOTileLinkIOConverter)(outerTLParams) val conv = Module(new NastiIOTileLinkIOConverter)(outerTLParams)
unwrap.io.in <> bank.outerTL unwrap.io.in <> bank.outerTL
conv.io.tl <> unwrap.io.out conv.io.tl <> unwrap.io.out
interconnect.io.masters(i) <> conv.io.nasti interconnect.io.masters(i) <> conv.io.nasti
@ -246,12 +251,12 @@ class OuterMemorySystem extends Module with TopLevelParameters {
for (i <- 0 until nTiles) { for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i" val csrName = s"conf:csr$i"
val csrPort = addrMap(csrName).port val csrPort = addrMap(csrName).port
val conv = Module(new SMIIONASTIIOConverter(xLen, pcrAddrBits)) val conv = Module(new SMIIONastiIOConverter(xLen, pcrAddrBits))
conv.io.nasti <> interconnect.io.slaves(csrPort) conv.io.nasti <> interconnect.io.slaves(csrPort)
io.pcr(i) <> conv.io.smi io.pcr(i) <> conv.io.smi
} }
val conv = Module(new SMIIONASTIIOConverter(xLen, scrAddrBits)) val conv = Module(new SMIIONastiIOConverter(xLen, scrAddrBits))
conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port) conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
io.scr <> conv.io.smi io.scr <> conv.io.smi
@ -260,9 +265,9 @@ class OuterMemorySystem extends Module with TopLevelParameters {
val mem_channels = interconnect.io.slaves.take(nMemChannels) val mem_channels = interconnect.io.slaves.take(nMemChannels)
// Create a SerDes for backup memory port // Create a SerDes for backup memory port
if(params(UseBackupMemoryPort)) { if(p(UseBackupMemoryPort)) {
VLSIUtils.doOuterMemorySystemSerdes( VLSIUtils.doOuterMemorySystemSerdes(
mem_channels, io.mem, io.mem_backup, io.mem_backup_en, mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
nMemChannels, params(HTIFWidth), params(CacheBlockOffsetBits)) nMemChannels, p(HTIFWidth), p(CacheBlockOffsetBits))
} else { io.mem <> mem_channels } } else { io.mem <> mem_channels }
} }

11
src/main/scala/Vlsi.scala
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@ -15,16 +15,17 @@ class MemDessert extends Module {
object VLSIUtils { object VLSIUtils {
def doOuterMemorySystemSerdes( def doOuterMemorySystemSerdes(
llcs: Seq[NASTIIO], llcs: Seq[NastiIO],
mems: Seq[NASTIIO], mems: Seq[NastiIO],
backup: MemSerializedIO, backup: MemSerializedIO,
en: Bool, en: Bool,
nMemChannels: Int, nMemChannels: Int,
htifWidth: Int, htifWidth: Int,
blockOffsetBits: Int) { blockOffsetBits: Int)
(implicit p: Parameters) {
val arb = Module(new NASTIArbiter(nMemChannels)) val arb = Module(new NastiArbiter(nMemChannels))
val conv = Module(new MemIONASTIIOConverter(blockOffsetBits)) val conv = Module(new MemIONastiIOConverter(blockOffsetBits))
val mem_serdes = Module(new MemSerdes(htifWidth)) val mem_serdes = Module(new MemSerdes(htifWidth))
conv.io.nasti <> arb.io.slave conv.io.nasti <> arb.io.slave

2
uncore

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Subproject commit 30c1dfe7722486eccf41cd2e0153de638724039e Subproject commit c533b99105a84d3969e9baccabf402fe7296711a