riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

refactor NASTI to not use param; new AddrMap class

Browse Source
This commit is contained in:
Henry Cook
2015-10-02 14:23:42 -07:00
parent c2ad0b7dd4
commit 3d10a89907
6 changed files with 70 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/main/scala/Vlsi.scala
View File

@ -15,16 +15,17 @@ class MemDessert extends Module {
object VLSIUtils {
def doOuterMemorySystemSerdes(
llcs: Seq[NASTIIO],
mems: Seq[NASTIIO],
llcs: Seq[NastiIO],
mems: Seq[NastiIO],
backup: MemSerializedIO,
en: Bool,
nMemChannels: Int,
htifWidth: Int,
blockOffsetBits: Int) {
blockOffsetBits: Int)
(implicit p: Parameters) {
val arb = Module(new NASTIArbiter(nMemChannels))
val conv = Module(new MemIONASTIIOConverter(blockOffsetBits))
val arb = Module(new NastiArbiter(nMemChannels))
val conv = Module(new MemIONastiIOConverter(blockOffsetBits))
val mem_serdes = Module(new MemSerdes(htifWidth))
conv.io.nasti <> arb.io.slave