fix make error mixing implicit and normal rules
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82cef6fa7b
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3ce8dbb6e5
@ -14,12 +14,12 @@ $(FIRRTL):
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.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
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$(firrtl) $(params_file) $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
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$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)"
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mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
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$(firrtl_debug) $(params_file_debug): $(chisel_srcs)
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$(generated_dir_debug)/%.$(MODEL).$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)"
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mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
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