riscv/rocket-chip
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Fix(?) SBT race by defining subproject build order

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This commit is contained in:
Andrew Waterman 2013-10-29 13:27:36 -07:00
parent 8c380a7c3a
commit 3c1d1f7981
1 changed files with 3 additions and 4 deletions
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7
project/build.scala
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@ -25,12 +25,11 @@ object BuildSettings extends Build {
//) //)
) )
lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket)
lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings) lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel) lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(hardfloat) lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha) lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket)
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")