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coreplex: allow buffer chains on certain bus ports

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This commit is contained in:
Henry Cook 2017-08-30 17:57:52 -07:00 committed by Wesley W. Terpstra
parent 57d0360c35
commit 3bde9506c6
7 changed files with 74 additions and 53 deletions
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10
src/main/scala/coreplex/FrontBus.scala
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@ -23,13 +23,9 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
fromSyncPorts(params, buffers, name)
def fromSyncPorts(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer")}}
for(i<-1 until buffers) {
buf(i).node :=* buf(i-1).node
}
inwardNode :=* buf(buffers-1).node
if(buffers>0) buf(0).node else inwardNode
val (in, out) = bufferChain(buffers, params, name)
inwardNode :=* out
in
}
def fromSyncFIFOMaster(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =

1
src/main/scala/coreplex/MemoryBus.scala
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@ -44,7 +44,6 @@ case object MemoryBusParams extends Field[MemoryBusParams]
/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) {
def fromCoherenceManager: TLInwardNode = inwardBufNode
def toDRAMController: TLOutwardNode = outwardBufNode
def toVariableWidthSlave: TLOutwardNode = outwardFragNode

2
src/main/scala/coreplex/PeripheryBus.scala
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@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
val pbus = new PeripheryBus(pbusParams)
// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
pbus.fromSystemBus := sbus.toPeripheryBus
pbus.fromSystemBus := sbus.toPeripheryBus(nBuffers = 4)
}

26
src/main/scala/coreplex/RocketCoreplex.scala
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@ -35,34 +35,34 @@ trait HasRocketTiles extends HasSystemBus
// Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
// according to the specified type of clock crossing.
val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex
val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, c), i) =>
val rocket_tiles: Seq[RocketTileWrapper] = wiringTuple.map { case ((lip, tp), i) =>
val pWithExtra = p.alterPartial {
case TileKey => c
case BuildRoCC => c.rocc
case TileKey => tp
case BuildRoCC => tp.rocc
case SharedMemoryTLEdge => sharedMemoryTLEdge
}
val wrapper = crossing match {
case SynchronousCrossing(params) => {
val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra))
sbus.fromSyncTiles(params) :=* wrapper.masterNode
val wrapper = LazyModule(new SyncRocketTile(tp, i)(pWithExtra))
sbus.fromSyncTiles(params, tp.externalBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.bufferToSlaves
wrapper
}
case AsynchronousCrossing(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
sbus.fromAsyncTiles(depth, sync) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, c.name)
val wrapper = LazyModule(new AsyncRocketTile(tp, i)(pWithExtra))
sbus.fromAsyncTiles(depth, sync, tp.externalBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name)
wrapper
}
case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
sbus.fromRationalTiles(direction) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toRationalSlaves(c.name)
val wrapper = LazyModule(new RationalRocketTile(tp, i)(pWithExtra))
sbus.fromRationalTiles(direction, tp.externalBuffers, tp.name) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name)
wrapper
}
}
c.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
tp.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
// Local Interrupts must be synchronized to the core clock
// before being passed into this module.
@ -77,7 +77,7 @@ trait HasRocketTiles extends HasSystemBus
val periphIntXbar = LazyModule(new IntXbar)
periphIntXbar.intnode := clint.intnode // msip+mtip
periphIntXbar.intnode := plic.intnode // meip
if (c.core.useVM) periphIntXbar.intnode := plic.intnode // seip
if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip
wrapper.periphIntNode := periphIntXbar.intnode
val coreIntXbar = LazyModule(new IntXbar)

71
src/main/scala/coreplex/SystemBus.scala
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@ -20,35 +20,28 @@ case object SystemBusParams extends Field[SystemBusParams]
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
master_splitter.suggestName(s"${busName}_master_TLSplitter"})
master_splitter.suggestName(s"${busName}_master_TLSplitter")
inwardNode :=* master_splitter.node
def busView = master_splitter.node.edgesIn.head
protected def inwardSplitNode: TLInwardNode = master_splitter.node
protected def outwardSplitNode: TLOutwardNode = master_splitter.node
private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
tile_fixer.suggestName(s"${busName}_tile_TLFIFOFixer")
private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
port_fixer.suggestName(s"${busName}_port_TLFIFOFixer")
master_splitter.node :=* port_fixer.node
private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
pbus_fixer.suggestName(s"${busName}_pbus_TLFIFOFixer")
master_splitter.node :=* tile_fixer.node
master_splitter.node :=* port_fixer.node
pbus_fixer.node :*= outwardWWNode
def toSplitSlaves: TLOutwardNode = outwardSplitNode
private val pbusBuffer0 = LazyModule(new TLBuffer(BufferParams.default))
private val pbusBuffer1 = LazyModule(new TLBuffer(BufferParams.default))
private val pbusBuffer2 = LazyModule(new TLBuffer(BufferParams.default))
private val pbusBuffer3 = LazyModule(new TLBuffer(BufferParams.default))
pbusBuffer0.node :*= pbus_fixer.node
pbusBuffer1.node :*= pbusBuffer0.node
pbusBuffer2.node :*= pbusBuffer1.node
pbusBuffer3.node :*= pbusBuffer2.node
val toPeripheryBus: TLOutwardNode = pbusBuffer3.node
def toPeripheryBus(nBuffers: Int): TLOutwardNode = {
val (in, out) = bufferChain(nBuffers, name = Some("PeripheryBus"))
in := pbus_fixer.node
out
}
val toMemoryBus: TLOutwardNode = outwardNode
@ -56,25 +49,43 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def fromCoherentChip: TLInwardNode = inwardNode
def fromSyncTiles(params: BufferParams, name: Option[String] = None): TLInwardNode = {
val buf = LazyModule(new TLBuffer(params))
name.foreach{n => buf.suggestName(s"${busName}_${n}_TLBuffer")}
tile_fixer.node :=* buf.node
buf.node
def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
val tile_buf = LazyModule(new TLBuffer(params))
name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") }
val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
val (in, out) = bufferChain(addBuffers, name = name)
master_splitter.node :=* out
in :=* tile_fixer.node
tile_fixer.node :=* tile_buf.node
tile_buf.node
}
def fromRationalTiles(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
val sink = LazyModule(new TLRationalCrossingSink(direction = dir))
name.foreach{n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink")}
tile_fixer.node :=* sink.node
sink.node
def fromRationalTiles(dir: RationalDirection, addBuffers: Int = 0, name: Option[String] = None): TLRationalInwardNode = {
val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir))
name.foreach{ n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
val (in, out) = bufferChain(addBuffers, name = name)
master_splitter.node :=* out
in :=* tile_fixer.node
tile_fixer.node :=* tile_sink.node
tile_sink.node
}
def fromAsyncTiles(depth: Int, sync: Int, name: Option[String] = None): TLAsyncInwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
name.foreach{n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossignSink")}
tile_fixer.node :=* sink.node
sink.node
def fromAsyncTiles(depth: Int, sync: Int, addBuffers: Int = 0, name: Option[String] = None): TLAsyncInwardNode = {
val tile_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
name.foreach { n => tile_fixer.suggestName(s"${busName}_${n}_TLFIFOFixer") }
val (in, out) = bufferChain(addBuffers, name = name)
master_splitter.node :=* out
in :=* tile_fixer.node
tile_fixer.node :=* tile_sink.node
tile_sink.node
}
def fromSyncPorts(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {

3
src/main/scala/tile/RocketTile.scala
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@ -19,7 +19,8 @@ case class RocketTileParams(
btb: Option[BTBParams] = Some(BTBParams()),
dataScratchpadBytes: Int = 0,
boundaryBuffers: Boolean = false,
name: Option[String] = Some("tile")) extends TileParams {
name: Option[String] = Some("tile"),
externalBuffers: Int = 0) extends TileParams {
require(icache.isDefined)
require(dcache.isDefined)
}

14
src/main/scala/tilelink/Bus.scala
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@ -32,6 +32,7 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
protected val xbar = LazyModule(new TLXbar)
xbar.suggestName(busName)
private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
master_buffer.suggestName(s"${busName}_master_TLBuffer")
private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
@ -66,6 +67,19 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
protected def inwardNode: TLInwardNode = xbar.node
protected def inwardBufNode: TLInwardNode = master_buffer.node
protected def bufferChain(n: Int, params: BufferParams = BufferParams.default, name: Option[String] = None): (TLInwardNode, TLOutwardNode) = {
if (n > 0) {
val chain = List.fill(n)(LazyModule(new TLBuffer(params)))
name.foreach { n => chain.zipWithIndex foreach { case(b, i) => b.suggestName(s"${busName}_${n}_${i}_TLBuffer") } }
(chain.init zip chain.tail) foreach { case(prev, next) => next.node :=* prev.node }
(chain.head.node, chain.last.node)
} else {
val dummy = LazyModule(new TLBuffer(BufferParams.none))
dummy.suggestName(s"${busName}_${n}_empty_TLBuffer")
(dummy.node, dummy.node)
}
}
def bufferFromMasters: TLInwardNode = inwardBufNode
def bufferToSlaves: TLOutwardNode = outwardBufNode